tests/opt/bug1854.ys

   1 read_verilog << EOT
   2 module top(input clk, input [3:0] addr, output reg [0:0] dout);
   3         reg [1:0] mem[0:15];
   4         initial begin
   5                 mem[0] = 2'b00;
   6                 mem[1] = 2'b01;
   7                 mem[2] = 2'b10;
   8                 mem[3] = 2'b11;
   9         end
  10         always @(posedge clk)
  11                 dout <= mem[addr];
  12 endmodule
  13 EOT
  14
  15 prep -rdff
  16
  17 select -assert-none t:$dff