Add ability to override verilog mode for verific -f command

[yosys.git] / tests / opt / bug2010.ys

read_verilog <<EOT
module test (
        input signed [1:0] n,
        output [3:0] dout
);
        assign dout = n + 4'sd 4;
endmodule
EOT

equiv_opt -assert opt -fine