tests/opt/bug2221.ys

   1 read_verilog <<EOT
   2 module test (
   3         input [1:0] a,
   4         input [1:0] b,
   5         output [5:0] y
   6 );
   7
   8 wire [5:0] aa = {a, 4'h0};
   9 wire [5:0] bb = {b, 4'h0};
  10
  11 assign y = aa * bb;
  12
  13 endmodule
  14 EOT
  15
  16 equiv_opt -assert opt_expr