tests/opt/bug2311.ys

   1 read_verilog -icells << EOT
   2
   3 module top(...);
   4
   5 input A;
   6 output Y;
   7
   8 $_XNOR_ x (.A(A), .B(A), .Y(Y));
   9
  10 endmodule
  11
  12 EOT
  13
  14 equiv_opt -assert opt_expr