tests/opt/bug2318.ys

   1 read_verilog <<EOT
   2 module t(input [3:0] A, input [3:0] B, output signed [3:0] Y);
   3
   4 wire [7:0] P = A * B;
   5 wire signed [7:0] SP = P;
   6 wire signed [3:0] SB = B;
   7 assign Y = SP / SB;
   8
   9 endmodule
  10 EOT
  11
  12 equiv_opt -assert peepopt