tests/opt/bug2765.ys

   1 read_verilog << EOT
   2
   3 module top(...);
   4
   5 input clk;
   6 input [3:0] wa;
   7 input [15:0] wd;
   8 input [3:0] ra;
   9 output [15:0] rd;
  10
  11 reg [15:0] mem[0:15];
  12
  13 integer i;
  14 reg x;
  15
  16 always @(posedge clk) begin
  17         for (i = 0; i < 2; i = i + 1) begin
  18                 x = i == 1;
  19                 if (x)
  20                         mem[wa] <= wd;
  21         end
  22 end
  23
  24 assign rd = mem[ra];
  25
  26 endmodule
  27
  28 EOT
  29
  30 proc
  31 opt
  32 select -assert-count 2 t:$memwr_v2
  33 opt_mem
  34 select -assert-count 1 t:$memwr_v2