tests/opt/bug2766.ys

   1 # Case 1.
   2
   3 read_verilog << EOT
   4
   5 module top(...);
   6
   7 input clk;
   8 input sel;
   9 input [3:0] ra;
  10 input [3:0] wa;
  11 input wd;
  12 output [3:0] rd;
  13
  14 reg [3:0] mem[0:15];
  15
  16 integer i;
  17 initial begin
  18         for (i = 0; i < 16; i = i + 1)
  19                 mem[i] <= i;
  20 end
  21
  22 assign rd = mem[ra];
  23
  24 always @(posedge clk) begin
  25         mem[wa] <= {4{sel ? wd : mem[wa][0]}};
  26 end
  27
  28 endmodule
  29
  30 EOT
  31
  32 hierarchy -auto-top
  33 proc
  34 opt_clean
  35
  36 design -save start
  37 memory_map
  38 design -save preopt
  39
  40 design -load start
  41 opt_mem_feedback
  42 memory_map
  43 design -save postopt
  44
  45 equiv_opt -assert -run prepare: :
  46
  47
  48
  49 design -reset
  50
  51 # Case 2.
  52
  53 read_verilog << EOT
  54
  55 module top(...);
  56
  57 input clk;
  58 input s1;
  59 input s2;
  60 input s3;
  61 input [3:0] ra;
  62 input [3:0] wa;
  63 input wd;
  64 output rd;
  65
  66 reg mem[0:15];
  67
  68 integer i;
  69 initial begin
  70         for (i = 0; i < 16; i = i + 1)
  71                 mem[i] <= ^i;
  72 end
  73
  74 assign rd = mem[ra];
  75
  76 wire ta = s1 ? wd : mem[wa];
  77 wire tb = s2 ? wd : ta;
  78 wire tc = s3 ? tb : ta;
  79
  80 always @(posedge clk) begin
  81         mem[wa] <= tc;
  82 end
  83
  84 endmodule
  85
  86 EOT
  87
  88 hierarchy -auto-top
  89 proc
  90 opt_clean
  91
  92 design -save start
  93 memory_map
  94 design -save preopt
  95
  96 design -load start
  97 opt_mem_feedback
  98 memory_map
  99 design -save postopt
 100
 101 equiv_opt -assert -run prepare: :