tests/opt/bug2824.ys

   1 read_verilog -icells << EOT
   2 module top(input I, output O);
   3 $pmux #(.WIDTH(1), .S_WIDTH(2)) m (.S({I, 1'b0}), .A(1'b0), .B({I, 1'b0}), .Y(O));
   4 endmodule
   5 EOT
   6
   7 equiv_opt -assert opt_muxtree