tests/opt/bug3047.ys

   1 read_verilog << EOT
   2
   3 module test (A, B, C, D, Y);
   4   input A, B, C, D;
   5   output Y;
   6   assign Y = A^B^C^D^A;
   7 endmodule
   8
   9 EOT
  10
  11 techmap
  12 equiv_opt -assert extract_reduce