tests/opt/opt_clean_mem.ys

   1 read_verilog <<EOT
   2 module top(...);
   3
   4 input [7:0] wa;
   5 input [7:0] ra1;
   6 input [7:0] ra2;
   7 input [7:0] wd;
   8 input clk;
   9 wire [7:0] rd1;
  10 wire [7:0] rd2;
  11
  12 reg [7:0] mem[0:7];
  13
  14 always @(posedge clk)
  15         mem[wa] <= wd;
  16 assign rd1 = mem[ra1];
  17 assign rd2 = mem[ra2];
  18
  19 initial mem[8'h12] = 8'h34;
  20
  21 endmodule
  22 EOT
  23
  24 proc
  25
  26 select -assert-count 2 t:$memrd
  27 select -assert-count 1 t:$memwr_v2
  28 select -assert-count 1 t:$meminit_v2
  29 design -save orig
  30
  31 opt_clean
  32 select -assert-none t:$memrd
  33 select -assert-none t:$memwr_v2
  34 select -assert-none t:$meminit_v2
  35
  36 design -load orig
  37 expose top/rd1
  38 opt_clean
  39 select -assert-count 1 t:$memrd
  40 select -assert-count 1 t:$memwr_v2
  41 select -assert-count 1 t:$meminit_v2
  42
  43 design -load orig
  44 expose top/rd1 top/rd2
  45 opt_clean
  46 select -assert-count 2 t:$memrd
  47 select -assert-count 1 t:$memwr_v2
  48 select -assert-count 1 t:$meminit_v2