tests/opt/opt_dff_en.ys

   1 ### Always-active EN removal.
   2
   3 read_verilog -icells <<EOT
   4
   5 module top(...);
   6
   7 input CLK;
   8 input [1:0] D;
   9 output [15:0] Q;
  10 input SRST;
  11 input ARST;
  12 input [1:0] CLR;
  13 input [1:0] SET;
  14
  15 $dffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(2)) ff0 (.CLK(CLK), .EN(1'b1), .D(D), .Q(Q[1:0]));
  16 $adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff1 (.CLK(CLK), .EN(1'b0), .ARST(ARST), .D(D), .Q(Q[3:2]));
  17 $sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(CLK), .EN(1'b1), .SRST(SRST), .D(D), .Q(Q[5:4]));
  18 $sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff3 (.CLK(CLK), .EN(1'b1), .SRST(SRST), .D(D), .Q(Q[7:6]));
  19 $dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff4 (.CLK(CLK), .EN(1'b0), .SET(SET), .CLR(CLR), .D(D), .Q(Q[9:8]));
  20
  21 $dlatch #(.EN_POLARITY(1'b1), .WIDTH(2)) ff5 (.EN(1'b1), .D(D), .Q(Q[11:10]));
  22 $adlatch #(.EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff6 (.EN(1'b0), .ARST(ARST), .D(D), .Q(Q[13:12]));
  23 $dlatchsr #(.EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff7 (.EN(1'b0), .SET(SET), .CLR(CLR), .D(D), .Q(Q[15:14]));
  24
  25 endmodule
  26
  27 EOT
  28
  29 design -save orig
  30
  31 # Equivalence check will fail for unmapped adlatch and dlatchsr due to negative hold hack.
  32 delete top/ff6 top/ff7
  33 equiv_opt -undef -assert -multiclock opt_dff
  34
  35 design -load orig
  36 delete top/ff6 top/ff7
  37 simplemap
  38 equiv_opt -undef -assert -multiclock opt_dff
  39
  40 design -load orig
  41 opt_dff
  42 select -assert-count 0 t:$dffe
  43 select -assert-count 0 t:$adffe
  44 select -assert-count 0 t:$sdffe
  45 select -assert-count 0 t:$sdffce
  46 select -assert-count 0 t:$dffsre
  47 select -assert-count 0 t:$dlatch
  48 select -assert-count 0 t:$adlatch
  49 select -assert-count 0 t:$dlatchsr
  50 select -assert-count 1 t:$dff
  51 select -assert-count 2 t:$sdff
  52 select -assert-count 1 t:$adff
  53 select -assert-count 1 t:$dffsr
  54
  55 design -load orig
  56 simplemap
  57 opt_dff
  58 select -assert-count 0 t:$_DFFE_*
  59 select -assert-count 0 t:$_SDFFE_*
  60 select -assert-count 0 t:$_SDFFCE_*
  61 select -assert-count 0 t:$_DFFSRE_*
  62 select -assert-count 0 t:$_DLATCH*
  63 select -assert-count 2 t:$_DFF_P_
  64 select -assert-count 4 t:$_SDFF_PP?_
  65 select -assert-count 2 t:$_DFF_PP?_
  66 select -assert-count 2 t:$_DFFSR_PNP_
  67
  68 design -reset
  69
  70
  71
  72 ### Never-active EN removal.
  73
  74 read_verilog -icells <<EOT
  75
  76 module top(...);
  77
  78 input CLK;
  79 input [1:0] D;
  80 (* init = 32'h55555555 *)
  81 output [31:0] Q;
  82 input SRST;
  83 input ARST;
  84 input [1:0] CLR;
  85 input [1:0] SET;
  86
  87 $dffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(2)) ff0 (.CLK(CLK), .EN(1'b0), .D(D), .Q(Q[1:0]));
  88 $adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff1 (.CLK(CLK), .EN(1'b1), .ARST(ARST), .D(D), .Q(Q[3:2]));
  89 $sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(CLK), .EN(1'b0), .SRST(SRST), .D(D), .Q(Q[5:4]));
  90 $sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff3 (.CLK(CLK), .EN(1'b0), .SRST(SRST), .D(D), .Q(Q[7:6]));
  91 $dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff4 (.CLK(CLK), .EN(1'b1), .SET(SET), .CLR(CLR), .D(D), .Q(Q[9:8]));
  92
  93 $dlatch #(.EN_POLARITY(1'b1), .WIDTH(2)) ff5 (.EN(1'b0), .D(D), .Q(Q[11:10]));
  94 $adlatch #(.EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff6 (.EN(1'b1), .ARST(ARST), .D(D), .Q(Q[13:12]));
  95 $dlatchsr #(.EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff7 (.EN(1'b1), .SET(SET), .CLR(CLR), .D(D), .Q(Q[15:14]));
  96
  97 $dffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(2)) ff8 (.CLK(CLK), .EN(1'bx), .D(D), .Q(Q[17:16]));
  98 $adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff9 (.CLK(CLK), .EN(1'bx), .ARST(ARST), .D(D), .Q(Q[19:18]));
  99 $sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff10 (.CLK(CLK), .EN(1'bx), .SRST(SRST), .D(D), .Q(Q[21:20]));
 100 $sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff11 (.CLK(CLK), .EN(1'bx), .SRST(SRST), .D(D), .Q(Q[23:22]));
 101 $dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff12 (.CLK(CLK), .EN(1'bx), .SET(SET), .CLR(CLR), .D(D), .Q(Q[25:24]));
 102
 103 $dlatch #(.EN_POLARITY(1'b1), .WIDTH(2)) ff13 (.EN(1'bx), .D(D), .Q(Q[27:26]));
 104 $adlatch #(.EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff14 (.EN(1'bx), .ARST(ARST), .D(D), .Q(Q[29:28]));
 105 $dlatchsr #(.EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff15 (.EN(1'bx), .SET(SET), .CLR(CLR), .D(D), .Q(Q[31:30]));
 106
 107 endmodule
 108
 109 EOT
 110
 111 design -save orig
 112
 113 equiv_opt -undef -assert -multiclock opt_dff
 114 design -load postopt
 115 select -assert-count 2 t:$dffe
 116 select -assert-count 4 t:$dlatch
 117 select -assert-count 4 t:$sr
 118 select -assert-none t:$dffe t:$dlatch t:$sr %% %n t:* %i
 119
 120 design -load orig
 121
 122 equiv_opt -undef -assert -multiclock opt_dff -keepdc
 123 design -load postopt
 124 select -assert-count 2 t:$dffe
 125 select -assert-count 1 t:$adffe
 126 select -assert-count 1 t:$sdffe
 127 select -assert-count 1 t:$sdffce
 128 select -assert-count 1 t:$dffsre
 129 select -assert-count 3 t:$dlatch
 130 select -assert-count 1 t:$adlatch
 131 select -assert-count 1 t:$dlatchsr
 132 select -assert-count 2 t:$sr
 133
 134 design -load orig
 135 simplemap
 136
 137 equiv_opt -undef -assert -multiclock opt_dff
 138 design -load postopt
 139 select -assert-count 4 t:$_DFFE_??_
 140 select -assert-count 8 t:$_DLATCH_?_
 141 select -assert-count 8 t:$_SR_??_
 142 select -assert-none t:$_DFFE_??_ t:$_DLATCH_?_ t:$_SR_??_ %% %n t:* %i
 143
 144 design -load orig
 145 simplemap
 146
 147 equiv_opt -undef -assert -multiclock opt_dff -keepdc
 148 design -load postopt
 149 select -assert-count 4 t:$_DFFE_??_
 150 select -assert-count 2 t:$_DFFE_????_
 151 select -assert-count 2 t:$_SDFFE_????_
 152 select -assert-count 2 t:$_SDFFCE_????_
 153 select -assert-count 2 t:$_DFFSRE_????_
 154 select -assert-count 6 t:$_DLATCH_?_
 155 select -assert-count 2 t:$_DLATCH_???_
 156 select -assert-count 2 t:$_DLATCHSR_???_
 157 select -assert-count 4 t:$_SR_??_