tests/opt/opt_dff_mux.ys

   1 ### CE and SRST matching.
   2
   3 read_verilog -icells <<EOT
   4
   5 module top(...);
   6
   7 input CLK;
   8 input NE, NS;
   9 input EN;
  10 output [23:0] Q;
  11 input [23:0] D;
  12 input SRST;
  13 input ARST;
  14 input [1:0] CLR;
  15 input [1:0] SET;
  16
  17 $dff #(.CLK_POLARITY(1'b1), .WIDTH(2)) ff0 (.CLK(CLK), .D(NS ? 2'h2 : NE ? D[1:0] : Q[1:0]), .Q(Q[1:0]));
  18 $dffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(2)) ff1 (.CLK(CLK), .EN(EN), .D(NS ? 2'h2 : NE ? D[3:2] : Q[3:2]), .Q(Q[3:2]));
  19 $adff #(.CLK_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(CLK), .ARST(ARST), .D(NS ? 2'h2 : NE ? D[5:4] : Q[5:4]), .Q(Q[5:4]));
  20 $adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff3 (.CLK(CLK), .EN(EN), .ARST(ARST), .D(NS ? 2'h2 : NE ? D[7:6] : Q[7:6]), .Q(Q[7:6]));
  21 $sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff4 (.CLK(CLK), .SRST(SRST), .D(NS ? 2'h2 : NE ? D[9:8] : Q[9:8]), .Q(Q[9:8]));
  22 $sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff5 (.CLK(CLK), .EN(EN), .SRST(SRST), .D(NS ? 2'h2 : NE ? D[11:10] : Q[11:10]), .Q(Q[11:10]));
  23 $sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff6 (.CLK(CLK), .EN(EN), .SRST(SRST), .D(NS ? 2'h2 : NE ? D[13:12] : Q[13:12]), .Q(Q[13:12]));
  24 $dffsr #(.CLK_POLARITY(1'b1), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff7 (.CLK(CLK), .SET(SET), .CLR(CLR), .D(NS ? 2'h2 : NE ? D[15:14] : Q[15:14]), .Q(Q[15:14]));
  25 $dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff8 (.CLK(CLK), .EN(EN), .SET(SET), .CLR(CLR), .D(NS ? 2'h2 : NE ? D[17:16] : Q[17:16]), .Q(Q[17:16]));
  26
  27 endmodule
  28
  29 EOT
  30
  31 design -save orig
  32
  33 equiv_opt -undef -assert -multiclock opt_dff -keepdc
  34 design -load postopt
  35 clean
  36 select -assert-count 0 t:$dff
  37 select -assert-count 0 t:$dffe
  38 select -assert-count 0 t:$adff
  39 select -assert-count 2 t:$adffe
  40 select -assert-count 0 t:$dffsr
  41 select -assert-count 2 t:$dffsre
  42 select -assert-count 0 t:$sdff
  43 select -assert-count 3 t:$sdffe
  44 select -assert-count 2 t:$sdffce
  45
  46 design -load orig
  47
  48 equiv_opt -undef -assert -multiclock opt_dff -nodffe -nosdff
  49 design -load postopt
  50 clean
  51 select -assert-count 1 t:$dff
  52 select -assert-count 1 t:$dffe
  53 select -assert-count 1 t:$adff
  54 select -assert-count 1 t:$adffe
  55 select -assert-count 1 t:$dffsr
  56 select -assert-count 1 t:$dffsre
  57 select -assert-count 1 t:$sdff
  58 select -assert-count 1 t:$sdffe
  59 select -assert-count 1 t:$sdffce
  60 equiv_opt -undef -assert -multiclock opt_dff -nodffe
  61 design -load postopt
  62 clean
  63 select -assert-count 0 t:$dff
  64 select -assert-count 0 t:$dffe
  65 select -assert-count 1 t:$adff
  66 select -assert-count 1 t:$adffe
  67 select -assert-count 1 t:$dffsr
  68 select -assert-count 1 t:$dffsre
  69 select -assert-count 2 t:$sdff
  70 select -assert-count 1 t:$sdffe
  71 select -assert-count 2 t:$sdffce
  72
  73 design -load orig
  74
  75 equiv_opt -undef -assert -multiclock opt_dff -nosdff
  76 design -load postopt
  77 clean
  78 select -assert-count 0 t:$dff
  79 select -assert-count 2 t:$dffe
  80 select -assert-count 0 t:$adff
  81 select -assert-count 2 t:$adffe
  82 select -assert-count 0 t:$dffsr
  83 select -assert-count 2 t:$dffsre
  84 select -assert-count 0 t:$sdff
  85 select -assert-count 2 t:$sdffe
  86 select -assert-count 1 t:$sdffce