tests/opt/opt_dff_sr.ys

   1 ### Always-active SET/CLR removal.
   2
   3 read_verilog -icells <<EOT
   4
   5 module top(...);
   6
   7 input CLK;
   8 input [5:0] D;
   9 output [23:0] Q;
  10 input CLR;
  11 input SET;
  12 input EN;
  13
  14 $dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR({CLR, CLR, CLR, 1'b1, 1'b0, 1'bx}), .SET({1'b1, 1'b0, 1'bx, SET, SET, SET}), .D(D), .Q(Q[5:0]));
  15 $dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .CLR({CLR, CLR, CLR, 1'b1, 1'b0, 1'bx}), .SET({1'b1, 1'b0, 1'bx, SET, SET, SET}), .D(D), .Q(Q[11:6]));
  16 $dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .CLR({CLR, CLR, CLR, 1'b1, 1'b0, 1'bx}), .SET({1'b1, 1'b0, 1'bx, SET, SET, SET}), .D(D), .Q(Q[17:12]));
  17 $sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR({CLR, CLR, CLR, 1'b1, 1'b0, 1'bx}), .SET({1'b1, 1'b0, 1'bx, SET, SET, SET}), .Q(Q[23:18]));
  18
  19 endmodule
  20
  21 EOT
  22
  23 design -save orig
  24
  25 # Equivalence check will fail for unmapped adlatch and dlatchsr due to negative hold hack.
  26 #equiv_opt -undef -assert -multiclock opt_dff
  27 #design -load postopt
  28 opt_dff
  29 select -assert-count 1 t:$dffsr
  30 select -assert-count 1 t:$dffsr r:WIDTH=2 %i
  31 select -assert-count 1 t:$dffsre
  32 select -assert-count 1 t:$dffsre r:WIDTH=2 %i
  33 select -assert-count 1 t:$dlatchsr
  34 select -assert-count 1 t:$dlatchsr r:WIDTH=2 %i
  35 select -assert-none t:$sr
  36
  37 design -load orig
  38
  39 #equiv_opt -undef -assert -multiclock opt_dff -keepdc
  40 #design -load postopt
  41 opt_dff -keepdc
  42 select -assert-count 1 t:$dffsr
  43 select -assert-count 1 t:$dffsr r:WIDTH=4 %i
  44 select -assert-count 1 t:$dffsre
  45 select -assert-count 1 t:$dffsre r:WIDTH=4 %i
  46 select -assert-count 1 t:$dlatchsr
  47 select -assert-count 1 t:$dlatchsr r:WIDTH=4 %i
  48 select -assert-count 1 t:$sr
  49 select -assert-count 1 t:$sr r:WIDTH=4 %i
  50
  51 design -load orig
  52 simplemap
  53
  54 #equiv_opt -undef -assert -multiclock opt_dff
  55 #design -load postopt
  56 opt_dff
  57 select -assert-count 1 t:$_DFF_PP0_
  58 select -assert-count 1 t:$_DFF_PP1_
  59 select -assert-count 1 t:$_DFFE_PN0P_
  60 select -assert-count 1 t:$_DFFE_PN1P_
  61 select -assert-count 1 t:$_DLATCH_PP0_
  62 select -assert-count 1 t:$_DLATCH_PN1_
  63 select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_DFFE_PN0P_ t:$_DFFE_PN1P_ t:$_DLATCH_PP0_ t:$_DLATCH_PN1_ t:$_NOT_ %% %n t:* %i
  64
  65 design -load orig
  66 simplemap
  67
  68 #equiv_opt -undef -assert -multiclock opt_dff -keepdc
  69 #design -load postopt
  70 opt_dff -keepdc
  71 select -assert-count 1 t:$_DFF_PP0_
  72 select -assert-count 1 t:$_DFF_PP1_
  73 select -assert-count 2 t:$_DFFSR_PPP_
  74 select -assert-count 1 t:$_DFFE_PN0P_
  75 select -assert-count 1 t:$_DFFE_PN1P_
  76 select -assert-count 2 t:$_DFFSRE_PNNP_
  77 select -assert-count 1 t:$_DLATCH_PP0_
  78 select -assert-count 1 t:$_DLATCH_PN1_
  79 select -assert-count 2 t:$_DLATCHSR_PNP_
  80 select -assert-count 1 t:$_DLATCH_P_
  81 select -assert-count 1 t:$_DLATCH_N_
  82 select -assert-count 2 t:$_SR_PN_
  83 select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_DFFSR_PPP_ t:$_DFFE_PN0P_ t:$_DFFE_PN1P_ t:$_DFFSRE_PNNP_ t:$_DLATCH_PP0_ t:$_DLATCH_PN1_ t:$_DLATCHSR_PNP_ t:$_NOT_ t:$_DLATCH_N_ t:$_DLATCH_P_ t:$_SR_PN_ %% %n t:* %i
  84
  85 design -reset
  86
  87
  88
  89 ### Never-active CLR removal.
  90
  91 read_verilog -icells <<EOT
  92
  93 module top(...);
  94
  95 input CLK;
  96 input [5:0] D;
  97 output [23:0] Q;
  98 input CLR;
  99 input SET;
 100 input EN;
 101
 102 $dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR(6'h00), .SET({6{SET}}), .D(D), .Q(Q[5:0]));
 103 $dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR(6'h3f), .SET({6{SET}}), .Q(Q[11:6]));
 104 $dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR(6'h00), .SET({6{SET}}), .Q(Q[17:12]));
 105 $sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR(6'h3f), .SET({6{SET}}), .Q(Q[23:18]));
 106
 107 endmodule
 108
 109 EOT
 110
 111 design -save orig
 112
 113 equiv_opt -undef -assert -multiclock opt_dff -keepdc
 114 design -load postopt
 115 select -assert-count 0 t:$dffsr
 116 select -assert-count 0 t:$dffsre
 117 select -assert-count 0 t:$dlatchsr
 118 select -assert-count 0 t:$sr
 119 select -assert-count 1 t:$adff
 120 select -assert-count 1 t:$adffe
 121 select -assert-count 1 t:$adlatch
 122 select -assert-count 1 t:$dlatch
 123
 124 design -reset
 125
 126
 127
 128 ### Never-active CLR removal (not applicable).
 129
 130 read_verilog -icells <<EOT
 131
 132 module top(...);
 133
 134 input CLK;
 135 input [5:0] D;
 136 output [23:0] Q;
 137 input CLR;
 138 input SET;
 139 input ALT;
 140 input EN;
 141
 142 $dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR(6'h00), .SET({{5{SET}}, ALT}), .D(D), .Q(Q[5:0]));
 143 $dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR(6'h3f), .SET({{5{SET}}, ALT}), .Q(Q[11:6]));
 144 $dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR(6'h00), .SET({{5{SET}}, ALT}), .Q(Q[17:12]));
 145 $sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR(6'h3f), .SET({{5{SET}}, ALT}), .Q(Q[23:18]));
 146
 147 endmodule
 148
 149 EOT
 150
 151 design -save orig
 152
 153 equiv_opt -undef -assert -multiclock opt_dff -keepdc
 154 design -load postopt
 155 select -assert-count 1 t:$dffsr
 156 select -assert-count 1 t:$dffsre
 157 select -assert-count 1 t:$dlatchsr
 158 select -assert-count 1 t:$sr
 159 select -assert-count 0 t:$adff
 160 select -assert-count 0 t:$adffe
 161 select -assert-count 0 t:$adlatch
 162 select -assert-count 0 t:$dlatch
 163
 164 design -load orig
 165 simplemap
 166
 167 equiv_opt -undef -assert -multiclock opt_dff -keepdc
 168 design -load postopt
 169 select -assert-count 0 t:$_DFFSR_*
 170 select -assert-count 0 t:$_DFFSRE_*
 171 select -assert-count 0 t:$_DLATCHSR_*
 172 select -assert-count 0 t:$_SR_*
 173 select -assert-count 6 t:$_DFF_PP1_
 174 select -assert-count 6 t:$_DFFE_PN1P_
 175 select -assert-count 6 t:$_DLATCH_PN1_
 176 select -assert-count 6 t:$_DLATCH_P_
 177
 178 design -reset
 179
 180
 181
 182 ### Never-active SET removal.
 183
 184 read_verilog -icells <<EOT
 185
 186 module top(...);
 187
 188 input CLK;
 189 input [5:0] D;
 190 output [23:0] Q;
 191 input CLR;
 192 input SET;
 193 input EN;
 194
 195 $dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR({6{CLR}}), .SET(6'h00), .D(D), .Q(Q[5:0]));
 196 $dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR({6{CLR}}), .SET(6'h3f), .Q(Q[11:6]));
 197 $dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR({6{CLR}}), .SET(6'h3f), .Q(Q[17:12]));
 198 $sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR({6{CLR}}), .SET(6'h00), .Q(Q[23:18]));
 199
 200 endmodule
 201
 202 EOT
 203
 204 design -save orig
 205
 206 equiv_opt -undef -assert -multiclock opt_dff -keepdc
 207 design -load postopt
 208 select -assert-count 0 t:$dffsr
 209 select -assert-count 0 t:$dffsre
 210 select -assert-count 0 t:$dlatchsr
 211 select -assert-count 0 t:$sr
 212 select -assert-count 1 t:$adff
 213 select -assert-count 1 t:$adffe
 214 select -assert-count 1 t:$adlatch
 215 select -assert-count 1 t:$dlatch
 216
 217 design -reset
 218
 219
 220
 221 ### Never-active CLR removal (not applicable).
 222
 223 read_verilog -icells <<EOT
 224
 225 module top(...);
 226
 227 input CLK;
 228 input [5:0] D;
 229 output [23:0] Q;
 230 input CLR;
 231 input SET;
 232 input ALT;
 233 input EN;
 234
 235 $dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR({{5{CLR}}, ALT}), .SET(6'h00), .D(D), .Q(Q[5:0]));
 236 $dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR({{5{CLR}}, ALT}), .SET(6'h3f), .Q(Q[11:6]));
 237 $dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR({{5{CLR}}, ALT}), .SET(6'h3f), .Q(Q[17:12]));
 238 $sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR({{5{CLR}}, ALT}), .SET(6'h00), .Q(Q[23:18]));
 239
 240 endmodule
 241
 242 EOT
 243
 244 design -save orig
 245
 246 equiv_opt -undef -assert -multiclock opt_dff -keepdc
 247 design -load postopt
 248 select -assert-count 1 t:$dffsr
 249 select -assert-count 1 t:$dffsre
 250 select -assert-count 1 t:$dlatchsr
 251 select -assert-count 1 t:$sr
 252 select -assert-count 0 t:$adff
 253 select -assert-count 0 t:$adffe
 254 select -assert-count 0 t:$adlatch
 255 select -assert-count 0 t:$dlatch
 256
 257 design -load orig
 258 simplemap
 259
 260 equiv_opt -undef -assert -multiclock opt_dff -keepdc
 261 design -load postopt
 262 select -assert-count 0 t:$_DFFSR_*
 263 select -assert-count 0 t:$_DFFSRE_*
 264 select -assert-count 0 t:$_DLATCHSR_*
 265 select -assert-count 0 t:$_SR_*
 266 select -assert-count 6 t:$_DFF_PP0_
 267 select -assert-count 6 t:$_DFFE_PN0P_
 268 select -assert-count 6 t:$_DLATCH_PP0_
 269 select -assert-count 6 t:$_DLATCH_N_
 270
 271 design -reset
 272
 273
 274
 275 ### SET/CLR merge into ARST.
 276
 277 read_verilog -icells <<EOT
 278
 279 module top(...);
 280
 281 input CLK;
 282 input [5:0] D;
 283 output [23:0] Q;
 284 input ARST;
 285 input EN;
 286
 287 $dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR({ARST, 5'h00}), .SET({1'b0, {5{ARST}}}), .D(D), .Q(Q[5:0]));
 288 $dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR({ARST, 5'h1f}), .SET({1'b1, {5{ARST}}}), .Q(Q[11:6]));
 289 $dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR({ARST, 5'h00}), .SET({1'b1, {5{ARST}}}), .Q(Q[17:12]));
 290 $sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR({ARST, 5'h1f}), .SET({1'b0, {5{ARST}}}), .Q(Q[23:18]));
 291
 292 endmodule
 293
 294 EOT
 295
 296 design -save orig
 297
 298 equiv_opt -undef -assert -multiclock opt_dff -keepdc
 299 design -load postopt
 300 select -assert-count 0 t:$dffsr
 301 select -assert-count 0 t:$dffsre
 302 select -assert-count 1 t:$dlatchsr
 303 select -assert-count 1 t:$sr
 304 select -assert-count 1 t:$adff
 305 select -assert-count 1 t:$adff r:ARST_VALUE=6'h1f %i
 306 select -assert-count 1 t:$adffe
 307 select -assert-count 1 t:$adffe r:ARST_VALUE=6'h1f %i
 308 select -assert-count 0 t:$adlatch
 309 select -assert-count 0 t:$dlatch