tests/opt/opt_dff_sr.ys

   1 ### Always-active SET/CLR removal.
   2
   3 read_verilog -icells <<EOT
   4
   5 module top(...);
   6
   7 input CLK;
   8 input [5:0] D;
   9 output [23:0] Q;
  10 input CLR;
  11 input SET;
  12 input EN;
  13
  14 $dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR({CLR, CLR, CLR, 1'b1, 1'b0, 1'bx}), .SET({1'b1, 1'b0, 1'bx, SET, SET, SET}), .D(D), .Q(Q[5:0]));
  15 $dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .CLR({CLR, CLR, CLR, 1'b1, 1'b0, 1'bx}), .SET({1'b1, 1'b0, 1'bx, SET, SET, SET}), .D(D), .Q(Q[11:6]));
  16 $dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .CLR({CLR, CLR, CLR, 1'b1, 1'b0, 1'bx}), .SET({1'b1, 1'b0, 1'bx, SET, SET, SET}), .D(D), .Q(Q[17:12]));
  17 $sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR({CLR, CLR, CLR, 1'b1, 1'b0, 1'bx}), .SET({1'b1, 1'b0, 1'bx, SET, SET, SET}), .Q(Q[23:18]));
  18
  19 endmodule
  20
  21 EOT
  22
  23 design -save orig
  24
  25 equiv_opt -undef -assert -multiclock opt_dff
  26 design -load postopt
  27 select -assert-count 1 t:$dffsr
  28 select -assert-count 1 t:$dffsr r:WIDTH=2 %i
  29 select -assert-count 1 t:$dffsre
  30 select -assert-count 1 t:$dffsre r:WIDTH=2 %i
  31 select -assert-count 1 t:$dlatchsr
  32 select -assert-count 1 t:$dlatchsr r:WIDTH=2 %i
  33 select -assert-none t:$sr
  34
  35 design -load orig
  36
  37 equiv_opt -undef -assert -multiclock opt_dff -keepdc
  38 design -load postopt
  39 select -assert-count 1 t:$dffsr
  40 select -assert-count 1 t:$dffsr r:WIDTH=4 %i
  41 select -assert-count 1 t:$dffsre
  42 select -assert-count 1 t:$dffsre r:WIDTH=4 %i
  43 select -assert-count 1 t:$dlatchsr
  44 select -assert-count 1 t:$dlatchsr r:WIDTH=4 %i
  45 select -assert-count 1 t:$sr
  46 select -assert-count 1 t:$sr r:WIDTH=4 %i
  47
  48 design -load orig
  49 simplemap
  50
  51 equiv_opt -undef -assert -multiclock opt_dff
  52 design -load postopt
  53 select -assert-count 1 t:$_DFF_PP0_
  54 select -assert-count 1 t:$_DFF_PP1_
  55 select -assert-count 1 t:$_DFFE_PN0P_
  56 select -assert-count 1 t:$_DFFE_PN1P_
  57 select -assert-count 1 t:$_DLATCH_PP0_
  58 select -assert-count 1 t:$_DLATCH_PN1_
  59 select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_DFFE_PN0P_ t:$_DFFE_PN1P_ t:$_DLATCH_PP0_ t:$_DLATCH_PN1_ t:$_NOT_ %% %n t:* %i
  60
  61 design -load orig
  62 simplemap
  63
  64 equiv_opt -undef -assert -multiclock opt_dff -keepdc
  65 design -load postopt
  66 select -assert-count 1 t:$_DFF_PP0_
  67 select -assert-count 1 t:$_DFF_PP1_
  68 select -assert-count 2 t:$_DFFSR_PPP_
  69 select -assert-count 1 t:$_DFFE_PN0P_
  70 select -assert-count 1 t:$_DFFE_PN1P_
  71 select -assert-count 2 t:$_DFFSRE_PNNP_
  72 select -assert-count 1 t:$_DLATCH_PP0_
  73 select -assert-count 1 t:$_DLATCH_PN1_
  74 select -assert-count 2 t:$_DLATCHSR_PNP_
  75 select -assert-count 1 t:$_DLATCH_P_
  76 select -assert-count 1 t:$_DLATCH_N_
  77 select -assert-count 2 t:$_SR_PN_
  78 select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_DFFSR_PPP_ t:$_DFFE_PN0P_ t:$_DFFE_PN1P_ t:$_DFFSRE_PNNP_ t:$_DLATCH_PP0_ t:$_DLATCH_PN1_ t:$_DLATCHSR_PNP_ t:$_NOT_ t:$_DLATCH_N_ t:$_DLATCH_P_ t:$_SR_PN_ %% %n t:* %i
  79
  80 design -reset
  81
  82
  83
  84 ### Never-active CLR removal.
  85
  86 read_verilog -icells <<EOT
  87
  88 module top(...);
  89
  90 input CLK;
  91 input [5:0] D;
  92 output [23:0] Q;
  93 input CLR;
  94 input SET;
  95 input EN;
  96
  97 $dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR(6'h00), .SET({6{SET}}), .D(D), .Q(Q[5:0]));
  98 $dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR(6'h3f), .SET({6{SET}}), .Q(Q[11:6]));
  99 $dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR(6'h00), .SET({6{SET}}), .Q(Q[17:12]));
 100 $sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR(6'h3f), .SET({6{SET}}), .Q(Q[23:18]));
 101
 102 endmodule
 103
 104 EOT
 105
 106 design -save orig
 107
 108 equiv_opt -undef -assert -multiclock opt_dff -keepdc
 109 design -load postopt
 110 select -assert-count 0 t:$dffsr
 111 select -assert-count 0 t:$dffsre
 112 select -assert-count 0 t:$dlatchsr
 113 select -assert-count 0 t:$sr
 114 select -assert-count 1 t:$adff
 115 select -assert-count 1 t:$adffe
 116 select -assert-count 1 t:$adlatch
 117 select -assert-count 1 t:$dlatch
 118
 119 design -reset
 120
 121
 122
 123 ### Never-active CLR removal (not applicable).
 124
 125 read_verilog -icells <<EOT
 126
 127 module top(...);
 128
 129 input CLK;
 130 input [5:0] D;
 131 output [23:0] Q;
 132 input CLR;
 133 input SET;
 134 input ALT;
 135 input EN;
 136
 137 $dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR(6'h00), .SET({{5{SET}}, ALT}), .D(D), .Q(Q[5:0]));
 138 $dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR(6'h3f), .SET({{5{SET}}, ALT}), .Q(Q[11:6]));
 139 $dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR(6'h00), .SET({{5{SET}}, ALT}), .Q(Q[17:12]));
 140 $sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR(6'h3f), .SET({{5{SET}}, ALT}), .Q(Q[23:18]));
 141
 142 endmodule
 143
 144 EOT
 145
 146 design -save orig
 147
 148 equiv_opt -undef -assert -multiclock opt_dff -keepdc
 149 design -load postopt
 150 select -assert-count 1 t:$dffsr
 151 select -assert-count 1 t:$dffsre
 152 select -assert-count 1 t:$dlatchsr
 153 select -assert-count 1 t:$sr
 154 select -assert-count 0 t:$adff
 155 select -assert-count 0 t:$adffe
 156 select -assert-count 0 t:$adlatch
 157 select -assert-count 0 t:$dlatch
 158
 159 design -load orig
 160 simplemap
 161
 162 equiv_opt -undef -assert -multiclock opt_dff -keepdc
 163 design -load postopt
 164 select -assert-count 0 t:$_DFFSR_*
 165 select -assert-count 0 t:$_DFFSRE_*
 166 select -assert-count 0 t:$_DLATCHSR_*
 167 select -assert-count 0 t:$_SR_*
 168 select -assert-count 6 t:$_DFF_PP1_
 169 select -assert-count 6 t:$_DFFE_PN1P_
 170 select -assert-count 6 t:$_DLATCH_PN1_
 171 select -assert-count 6 t:$_DLATCH_P_
 172
 173 design -reset
 174
 175
 176
 177 ### Never-active SET removal.
 178
 179 read_verilog -icells <<EOT
 180
 181 module top(...);
 182
 183 input CLK;
 184 input [5:0] D;
 185 output [23:0] Q;
 186 input CLR;
 187 input SET;
 188 input EN;
 189
 190 $dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR({6{CLR}}), .SET(6'h00), .D(D), .Q(Q[5:0]));
 191 $dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR({6{CLR}}), .SET(6'h3f), .Q(Q[11:6]));
 192 $dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR({6{CLR}}), .SET(6'h3f), .Q(Q[17:12]));
 193 $sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR({6{CLR}}), .SET(6'h00), .Q(Q[23:18]));
 194
 195 endmodule
 196
 197 EOT
 198
 199 design -save orig
 200
 201 equiv_opt -undef -assert -multiclock opt_dff -keepdc
 202 design -load postopt
 203 select -assert-count 0 t:$dffsr
 204 select -assert-count 0 t:$dffsre
 205 select -assert-count 0 t:$dlatchsr
 206 select -assert-count 0 t:$sr
 207 select -assert-count 1 t:$adff
 208 select -assert-count 1 t:$adffe
 209 select -assert-count 1 t:$adlatch
 210 select -assert-count 1 t:$dlatch
 211
 212 design -reset
 213
 214
 215
 216 ### Never-active CLR removal (not applicable).
 217
 218 read_verilog -icells <<EOT
 219
 220 module top(...);
 221
 222 input CLK;
 223 input [5:0] D;
 224 output [23:0] Q;
 225 input CLR;
 226 input SET;
 227 input ALT;
 228 input EN;
 229
 230 $dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR({{5{CLR}}, ALT}), .SET(6'h00), .D(D), .Q(Q[5:0]));
 231 $dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR({{5{CLR}}, ALT}), .SET(6'h3f), .Q(Q[11:6]));
 232 $dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR({{5{CLR}}, ALT}), .SET(6'h3f), .Q(Q[17:12]));
 233 $sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR({{5{CLR}}, ALT}), .SET(6'h00), .Q(Q[23:18]));
 234
 235 endmodule
 236
 237 EOT
 238
 239 design -save orig
 240
 241 equiv_opt -undef -assert -multiclock opt_dff -keepdc
 242 design -load postopt
 243 select -assert-count 1 t:$dffsr
 244 select -assert-count 1 t:$dffsre
 245 select -assert-count 1 t:$dlatchsr
 246 select -assert-count 1 t:$sr
 247 select -assert-count 0 t:$adff
 248 select -assert-count 0 t:$adffe
 249 select -assert-count 0 t:$adlatch
 250 select -assert-count 0 t:$dlatch
 251
 252 design -load orig
 253 simplemap
 254
 255 equiv_opt -undef -assert -multiclock opt_dff -keepdc
 256 design -load postopt
 257 select -assert-count 0 t:$_DFFSR_*
 258 select -assert-count 0 t:$_DFFSRE_*
 259 select -assert-count 0 t:$_DLATCHSR_*
 260 select -assert-count 0 t:$_SR_*
 261 select -assert-count 6 t:$_DFF_PP0_
 262 select -assert-count 6 t:$_DFFE_PN0P_
 263 select -assert-count 6 t:$_DLATCH_PP0_
 264 select -assert-count 6 t:$_DLATCH_N_
 265
 266 design -reset
 267
 268
 269
 270 ### SET/CLR merge into ARST.
 271
 272 read_verilog -icells <<EOT
 273
 274 module top(...);
 275
 276 input CLK;
 277 input [5:0] D;
 278 output [23:0] Q;
 279 input ARST;
 280 input EN;
 281
 282 $dffsr #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b1), .CLR_POLARITY(1'b1), .WIDTH(6)) ff0 (.CLK(CLK), .CLR({ARST, 5'h00}), .SET({1'b0, {5{ARST}}}), .D(D), .Q(Q[5:0]));
 283 $dffsre #(.CLK_POLARITY(1'b1), .SET_POLARITY(1'b0), .CLR_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(6)) ff1 (.CLK(CLK), .EN(EN), .D(D), .CLR({ARST, 5'h1f}), .SET({1'b1, {5{ARST}}}), .Q(Q[11:6]));
 284 $dlatchsr #(.SET_POLARITY(1'b0), .CLR_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(6)) ff2 (.EN(EN), .D(D), .CLR({ARST, 5'h00}), .SET({1'b1, {5{ARST}}}), .Q(Q[17:12]));
 285 $sr #(.SET_POLARITY(1'b1), .CLR_POLARITY(1'b0), .WIDTH(6)) ff3 (.CLR({ARST, 5'h1f}), .SET({1'b0, {5{ARST}}}), .Q(Q[23:18]));
 286
 287 endmodule
 288
 289 EOT
 290
 291 design -save orig
 292
 293 equiv_opt -undef -assert -multiclock opt_dff -keepdc
 294 design -load postopt
 295 select -assert-count 0 t:$dffsr
 296 select -assert-count 0 t:$dffsre
 297 select -assert-count 1 t:$dlatchsr
 298 select -assert-count 1 t:$sr
 299 select -assert-count 1 t:$adff
 300 select -assert-count 1 t:$adff r:ARST_VALUE=6'h1f %i
 301 select -assert-count 1 t:$adffe
 302 select -assert-count 1 t:$adffe r:ARST_VALUE=6'h1f %i
 303 select -assert-count 0 t:$adlatch
 304 select -assert-count 0 t:$dlatch