tests/opt/opt_dff_srst.ys

   1 ### Always-active SRST removal.
   2
   3 read_verilog -icells <<EOT
   4
   5 module top(...);
   6
   7 input CLK;
   8 input [1:0] D;
   9 (* init=12'h555 *)
  10 output [11:0] Q;
  11 input SRST;
  12 input EN;
  13
  14 $sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff0 (.CLK(CLK), .SRST(1'b1), .D(D), .Q(Q[1:0]));
  15 $sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff1 (.CLK(CLK), .SRST(1'b0), .EN(EN), .D(D), .Q(Q[3:2]));
  16 $sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(CLK), .SRST(1'b0), .EN(EN), .D(D), .Q(Q[5:4]));
  17 $sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff3 (.CLK(CLK), .SRST(1'bx), .D(D), .Q(Q[7:6]));
  18 $sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff4 (.CLK(CLK), .SRST(1'bx), .EN(EN), .D(D), .Q(Q[9:8]));
  19 $sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff5 (.CLK(CLK), .SRST(1'bx), .EN(EN), .D(D), .Q(Q[11:10]));
  20
  21
  22 endmodule
  23
  24 EOT
  25
  26 design -save orig
  27
  28 equiv_opt -undef -assert -multiclock opt_dff
  29 design -load postopt
  30 select -assert-count 0 t:$sdff
  31 select -assert-count 0 t:$sdffe
  32 select -assert-count 0 t:$sdffce
  33 select -assert-count 4 t:$dff
  34 select -assert-count 2 t:$dffe
  35
  36 design -load orig
  37
  38 equiv_opt -undef -assert -multiclock opt_dff -keepdc
  39 design -load postopt
  40 select -assert-count 1 t:$sdff
  41 select -assert-count 1 t:$sdffe
  42 select -assert-count 1 t:$sdffce
  43 select -assert-count 2 t:$dff
  44 select -assert-count 1 t:$dffe
  45
  46 design -load orig
  47 simplemap
  48
  49 equiv_opt -undef -assert -multiclock opt_dff
  50 design -load postopt
  51 select -assert-none t:$_SDFF_???_
  52 select -assert-none t:$_SDFFE_????_
  53 select -assert-none t:$_SDFFCE_????_
  54 select -assert-count 8 t:$_DFF_?_
  55 select -assert-count 4 t:$_DFFE_??_
  56
  57 design -load orig
  58 simplemap
  59
  60 equiv_opt -undef -assert -multiclock opt_dff -keepdc
  61 design -load postopt
  62 select -assert-count 2 t:$_SDFF_???_
  63 select -assert-count 2 t:$_SDFFE_????_
  64 select -assert-count 2 t:$_SDFFCE_????_
  65 select -assert-count 4 t:$_DFF_?_
  66 select -assert-count 2 t:$_DFFE_??_
  67
  68 design -reset
  69
  70
  71 ### Never-active SRST removal.
  72
  73 read_verilog -icells <<EOT
  74
  75 module top(...);
  76
  77 input CLK;
  78 input [1:0] D;
  79 output [5:0] Q;
  80 input SRST;
  81 input EN;
  82
  83 $sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff0 (.CLK(CLK), .SRST(1'b0), .D(D), .Q(Q[1:0]));
  84 $sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff1 (.CLK(CLK), .SRST(1'b1), .EN(EN), .D(D), .Q(Q[3:2]));
  85 $sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(CLK), .SRST(1'b1), .EN(EN), .D(D), .Q(Q[5:4]));
  86
  87 endmodule
  88
  89 EOT
  90
  91 design -save orig
  92
  93 equiv_opt -undef -assert -multiclock opt_dff
  94 design -load postopt
  95 select -assert-none t:$sdff
  96 select -assert-none t:$sdffe
  97 select -assert-none t:$sdffce
  98 select -assert-count 1 t:$dff
  99 select -assert-count 2 t:$dffe
 100
 101 design -load orig
 102 simplemap
 103
 104 equiv_opt -undef -assert -multiclock opt_dff
 105 design -load postopt
 106 select -assert-none t:$_SDFF_???_
 107 select -assert-none t:$_SDFFE_????_
 108 select -assert-none t:$_SDFFCE_????_
 109 select -assert-count 2 t:$_DFF_P_
 110 select -assert-count 4 t:$_DFFE_PP_
 111
 112 design -reset
 113