tests/opt/opt_expr.ys

   1
   2 read_verilog <<EOT
   3 module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
   4     assign o = (i << 4) + j;
   5 endmodule
   6 EOT
   7
   8 equiv_opt -assert opt_expr -fine
   9 design -load postopt
  10
  11 select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
  12
  13 ##########
  14
  15 # alumacc version of above
  16 design -reset
  17 read_verilog <<EOT
  18 module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
  19     assign o = (i << 4) + j;
  20 endmodule
  21 EOT
  22
  23 alumacc
  24 equiv_opt -assert opt_expr -fine
  25 design -load postopt
  26
  27 select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
  28
  29 ##########
  30
  31 design -reset
  32 read_verilog <<EOT
  33 module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
  34     assign o = (i << 4) + j;
  35 endmodule
  36 EOT
  37
  38 equiv_opt -assert opt_expr -fine
  39 design -load postopt
  40
  41 select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
  42
  43 ##########
  44
  45 # alumacc version of above
  46 design -reset
  47 read_verilog <<EOT
  48 module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
  49     assign o = (i << 4) + j;
  50 endmodule
  51 EOT
  52
  53 alumacc
  54 equiv_opt -assert opt_expr -fine
  55 design -load postopt
  56
  57 select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
  58
  59 ##########
  60
  61 design -reset
  62 read_verilog <<EOT
  63 module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
  64     assign o = j - (i << 4);
  65 endmodule
  66 EOT
  67
  68 equiv_opt -assert opt_expr -fine
  69 design -load postopt
  70
  71 select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
  72
  73 ##########
  74
  75 # alumacc version of above
  76 design -reset
  77 read_verilog <<EOT
  78 module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
  79     assign o = j - (i << 4);
  80 endmodule
  81 EOT
  82
  83 alumacc
  84 equiv_opt -assert opt_expr -fine
  85 design -load postopt
  86
  87 dump
  88 select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
  89
  90 ##########
  91
  92 design -reset
  93 read_verilog <<EOT
  94 module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
  95     assign o = j - (i << 4);
  96 endmodule
  97 EOT
  98
  99 equiv_opt -assert opt_expr -fine
 100 design -load postopt
 101
 102 select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
 103
 104 ##########
 105
 106 # alumacc version of above
 107 design -reset
 108 read_verilog <<EOT
 109 module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
 110     assign o = j - (i << 4);
 111 endmodule
 112 EOT
 113
 114 alumacc
 115 equiv_opt -assert opt_expr -fine
 116 design -load postopt
 117
 118 select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
 119
 120 ##########
 121
 122 design -reset
 123 read_verilog <<EOT
 124 module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
 125     assign o = (i << 4) - j;
 126 endmodule
 127 EOT
 128
 129 equiv_opt -assert opt_expr -fine
 130 design -load postopt
 131
 132 select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
 133
 134 ##########
 135
 136 # alumacc version of above
 137 design -reset
 138 read_verilog <<EOT
 139 module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
 140     assign o = (i << 4) - j;
 141 endmodule
 142 EOT
 143
 144 alumacc
 145 opt_expr -fine
 146 equiv_opt -assert opt_expr -fine
 147 design -load postopt
 148
 149 select -assert-count 1 t:$alu r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
 150
 151 ##########
 152
 153 design -reset
 154 read_verilog <<EOT
 155 module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
 156     assign o = 5'b00010 - i;
 157 endmodule
 158 EOT
 159
 160 wreduce
 161 equiv_opt -assert opt_expr -fine
 162 design -load postopt
 163
 164 select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 165
 166 ##########
 167
 168 # alumacc version of above
 169 design -reset
 170 read_verilog <<EOT
 171 module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
 172     assign o = 5'b00010 - i;
 173 endmodule
 174 EOT
 175
 176 wreduce
 177 alumacc
 178 equiv_opt -assert opt_expr -fine
 179 design -load postopt
 180
 181 select -assert-count 1 t:$alu r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 182
 183 ###########
 184
 185 design -reset
 186 read_verilog -icells <<EOT
 187 module opt_expr_alu_test_ci0_bi0(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
 188     \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b0), .X(x), .Y(y), .CO(co));
 189 endmodule
 190 EOT
 191 check
 192
 193 equiv_opt -assert opt_expr -fine
 194 design -load postopt
 195 select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 196
 197 ###########
 198
 199 design -reset
 200 read_verilog -icells <<EOT
 201 module opt_expr_alu_test_ci1_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
 202     \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b1), .BI(1'b1), .X(x), .Y(y), .CO(co));
 203 endmodule
 204 EOT
 205 check
 206
 207 equiv_opt -assert opt_expr -fine
 208 design -load postopt
 209 select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 210
 211 ###########
 212
 213 design -reset
 214 read_verilog -icells <<EOT
 215 module opt_expr_alu_test_ci0_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
 216     \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b1), .X(x), .Y(y), .CO(co));
 217 endmodule
 218 EOT
 219 check
 220
 221 equiv_opt -assert opt_expr -fine
 222 design -load postopt
 223 select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
 224
 225 ###########
 226
 227 design -reset
 228 read_verilog -icells <<EOT
 229 module opt_expr_shiftx_1bit(input [2:0] a, input [1:0] b, output y);
 230     \$shiftx #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) shiftx (.A({1'bx,a}), .B(b), .Y(y));
 231 endmodule
 232 EOT
 233 check
 234
 235 equiv_opt -assert opt_expr
 236 design -load postopt
 237 select -assert-count 1 t:$shiftx r:A_WIDTH=3 %i
 238
 239 ###########
 240
 241 design -reset
 242 read_verilog -icells <<EOT
 243 module opt_expr_shiftx_3bit(input [9:0] a, input [3:0] b, output [2:0] y);
 244     \$shiftx #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shiftx (.A({4'bxx00,a}), .B(b), .Y(y));
 245 endmodule
 246 EOT
 247 check
 248
 249 equiv_opt -assert opt_expr
 250 design -load postopt
 251 select -assert-count 1 t:$shiftx r:A_WIDTH=12 %i
 252
 253 ###########
 254
 255 design -reset
 256 read_verilog -icells <<EOT
 257 module opt_expr_shift_1bit(input [2:0] a, input [1:0] b, output y);
 258     \$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) shift (.A({1'b0,a}), .B(b), .Y(y));
 259 endmodule
 260 EOT
 261 check
 262
 263 equiv_opt -assert opt_expr
 264 design -load postopt
 265 select -assert-count 1 t:$shift r:A_WIDTH=3 %i
 266
 267 ###########
 268
 269 design -reset
 270 read_verilog -icells <<EOT
 271 module opt_expr_shift_3bit(input [9:0] a, input [3:0] b, output [2:0] y);
 272     \$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shift (.A({4'b0x0x,a}), .B(b), .Y(y));
 273 endmodule
 274 EOT
 275 check
 276
 277 equiv_opt -assert opt_expr
 278 design -load postopt
 279 select -assert-count 1 t:$shift r:A_WIDTH=10 %i
 280
 281 ###########
 282
 283 design -reset
 284 read_verilog -icells <<EOT
 285 module opt_expr_shift_3bit_keepdc(input [9:0] a, input [3:0] b, output [2:0] y);
 286     \$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shift (.A({4'b0x0x,a}), .B(b), .Y(y));
 287 endmodule
 288 EOT
 289 check
 290
 291 equiv_opt -assert opt_expr -keepdc
 292 design -load postopt
 293 select -assert-count 1 t:$shift r:A_WIDTH=13 %i
 294
 295 ###########
 296
 297 design -reset
 298 read_verilog -icells <<EOT
 299 module opt_expr_mul_low_bits(input [2:0] a, input [2:0] b, output [7:0] y);
 300     \$mul #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(8)) mul (.A({a, 1'b0}), .B({b, 1'b0}), .Y(y));
 301 endmodule
 302 EOT
 303 check
 304
 305 equiv_opt -assert opt_expr
 306 design -load postopt
 307 select -assert-count 1 t:$mul r:A_WIDTH=3 %i r:B_WIDTH=3 %i r:Y_WIDTH=6 %i
 308
 309 ###########
 310
 311 design -reset
 312 read_verilog -icells <<EOT
 313 module opt_expr_mul_low_bits(input [2:0] a, input [2:0] b, output [7:0] y);
 314     \$mul #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(8)) mul (.A({a, 1'b0}), .B({b, 1'b0}), .Y(y));
 315 endmodule
 316 EOT
 317 check
 318
 319 equiv_opt -assert opt_expr -keepdc
 320 design -load postopt
 321 select -assert-count 1 t:$mul r:A_WIDTH=4 %i r:B_WIDTH=4 %i r:Y_WIDTH=8 %i