3 module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
4 assign o = (i << 4) + j;
8 equiv_opt -assert opt_expr -fine
11 select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
15 # alumacc version of above
18 module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
19 assign o = (i << 4) + j;
24 equiv_opt -assert opt_expr -fine
27 select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
33 module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
34 assign o = (i << 4) + j;
38 equiv_opt -assert opt_expr -fine
41 select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
45 # alumacc version of above
48 module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
49 assign o = (i << 4) + j;
54 equiv_opt -assert opt_expr -fine
57 select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
63 module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
64 assign o = j - (i << 4);
68 equiv_opt -assert opt_expr -fine
71 select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
75 # alumacc version of above
78 module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
79 assign o = j - (i << 4);
84 equiv_opt -assert opt_expr -fine
88 select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
94 module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
95 assign o = j - (i << 4);
99 equiv_opt -assert opt_expr -fine
102 select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
106 # alumacc version of above
109 module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
110 assign o = j - (i << 4);
115 equiv_opt -assert opt_expr -fine
118 select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
124 module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
125 assign o = (i << 4) - j;
129 equiv_opt -assert opt_expr -fine
132 select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
136 # alumacc version of above
139 module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
140 assign o = (i << 4) - j;
146 equiv_opt -assert opt_expr -fine
149 select -assert-count 1 t:$alu r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
155 module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
156 assign o = 5'b00010 - i;
161 equiv_opt -assert opt_expr -fine
164 select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
168 # alumacc version of above
171 module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
172 assign o = 5'b00010 - i;
178 equiv_opt -assert opt_expr -fine
181 select -assert-count 1 t:$alu r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
186 read_verilog -icells <<EOT
187 module opt_expr_alu_test_ci0_bi0(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
188 \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b0), .X(x), .Y(y), .CO(co));
193 equiv_opt -assert opt_expr -fine
195 select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
200 read_verilog -icells <<EOT
201 module opt_expr_alu_test_ci1_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
202 \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b1), .BI(1'b1), .X(x), .Y(y), .CO(co));
207 equiv_opt -assert opt_expr -fine
209 select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
214 read_verilog -icells <<EOT
215 module opt_expr_alu_test_ci0_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
216 \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b1), .X(x), .Y(y), .CO(co));
221 equiv_opt -assert opt_expr -fine
223 select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
228 read_verilog -icells <<EOT
229 module opt_expr_shiftx_1bit(input [2:0] a, input [1:0] b, output y);
230 \$shiftx #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) shiftx (.A({1'bx,a}), .B(b), .Y(y));
235 equiv_opt -assert opt_expr
237 select -assert-count 1 t:$shiftx r:A_WIDTH=3 %i
242 read_verilog -icells <<EOT
243 module opt_expr_shiftx_3bit(input [9:0] a, input [3:0] b, output [2:0] y);
244 \$shiftx #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shiftx (.A({4'bxx00,a}), .B(b), .Y(y));
249 equiv_opt -assert opt_expr
251 select -assert-count 1 t:$shiftx r:A_WIDTH=12 %i
256 read_verilog -icells <<EOT
257 module opt_expr_shift_1bit(input [2:0] a, input [1:0] b, output y);
258 \$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) shift (.A({1'b0,a}), .B(b), .Y(y));
263 equiv_opt -assert opt_expr
265 select -assert-count 1 t:$shift r:A_WIDTH=3 %i
270 read_verilog -icells <<EOT
271 module opt_expr_shift_3bit(input [9:0] a, input [3:0] b, output [2:0] y);
272 \$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shift (.A({4'b0x0x,a}), .B(b), .Y(y));
277 equiv_opt -assert opt_expr
279 select -assert-count 1 t:$shift r:A_WIDTH=10 %i
284 read_verilog -icells <<EOT
285 module opt_expr_shift_3bit_keepdc(input [9:0] a, input [3:0] b, output [2:0] y);
286 \$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shift (.A({4'b0x0x,a}), .B(b), .Y(y));
291 equiv_opt -assert opt_expr -keepdc
293 select -assert-count 1 t:$shift r:A_WIDTH=13 %i