tests/opt/opt_expr_alu.ys

   1 read_verilog <<EOT
   2 module test(input a, output [1:0] y);
   3 assign y = {a,1'b0} + 1'b1;
   4 endmodule
   5 EOT
   6
   7 alumacc
   8 equiv_opt -assert opt_expr -fine
   9 design -load postopt
  10 select -assert-count 1 t:$pos
  11 select -assert-none t:$pos t:* %D
  12
  13
  14 design -reset
  15 read_verilog <<EOT
  16 module test(input a, output [1:0] y);
  17 assign y = {a,1'b1} + 1'b1;
  18 endmodule
  19 EOT
  20
  21 alumacc
  22 select -assert-count 1 t:$alu
  23 select -assert-none t:$alu t:* %D
  24
  25
  26 design -reset
  27 read_verilog <<EOT
  28 module test(input a, output [1:0] y);
  29 assign y = {a,1'b1} - 1'b1;
  30 endmodule
  31 EOT
  32
  33 equiv_opt -assert opt_expr -fine
  34 design -load postopt
  35 select -assert-count 1 t:$pos
  36 select -assert-none t:$pos t:* %D
  37
  38
  39 design -reset
  40 read_verilog <<EOT
  41 module test(input a, output [3:0] y);
  42 assign y = {a,3'b101} - 1'b1;
  43 endmodule
  44 EOT
  45
  46 equiv_opt -assert opt_expr -fine
  47 design -load postopt
  48 select -assert-count 1 t:$pos
  49 select -assert-none t:$pos t:* %D
  50
  51
  52 design -reset
  53 read_verilog <<EOT
  54 module test(input a, output [3:0] y);
  55 assign y = {a,3'b101} - 1'b1;
  56 endmodule
  57 EOT
  58
  59 alumacc
  60 equiv_opt -assert opt_expr -fine
  61 design -load postopt
  62 select -assert-count 1 t:$not
  63 select -assert-none t:$not %% t:* %D
  64
  65
  66 design -reset
  67 read_verilog <<EOT
  68 module test(input [1:0] a, output [3:0] y);
  69 assign y = -{a[1], 2'b10, a[0]};
  70 endmodule
  71 EOT
  72
  73 alumacc
  74 equiv_opt -assert opt -fine
  75 design -load postopt
  76 select -assert-count 1 t:$alu
  77 select -assert-count 1 t:$alu r:Y_WIDTH=3 %i
  78 select -assert-count 1 t:$not
  79 select -assert-none t:$alu t:$not t:* %D %D
  80
  81
  82 design -reset
  83 read_verilog <<EOT
  84 module test(input [3:0] a, input [2:0] b, output [5:0] y);
  85 assign y = {a[3:2], 1'b1, a[1:0]} + {b[2], 2'b11, b[1:0]};
  86 endmodule
  87 EOT
  88
  89 alumacc
  90 equiv_opt -assert opt -fine
  91 design -load postopt
  92 dump
  93 select -assert-count 2 t:$alu
  94 select -assert-count 1 t:$alu r:Y_WIDTH=2 %i
  95 select -assert-count 1 t:$alu r:Y_WIDTH=3 %i
  96 select -assert-none t:$alu t:* %D
  97
  98
  99 design -reset
 100 read_verilog <<EOT
 101 module test(input [3:0] a, input [3:0] b, output [5:0] y);
 102 assign y = {a[3:2], 1'b0, a[1:0]} + {b[3:2], 1'b0, b[1:0]};
 103 endmodule
 104 EOT
 105
 106 alumacc
 107 equiv_opt -assert opt -fine
 108 design -load postopt
 109 select -assert-count 2 t:$alu
 110 select -assert-count 2 t:$alu r:Y_WIDTH=3 %i
 111 select -assert-none t:$alu t:* %D
 112
 113
 114 design -reset
 115 read_verilog -icells <<EOT
 116 module test(input [3:0] a, output [3:0] y, output [3:0] x, output [3:0] co);
 117 $alu #(
 118         .A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
 119         .A_SIGNED(0), .B_SIGNED(0),
 120 ) alu (
 121         .A(a), .B(4'h0),
 122         .BI(1'b0), .CI(1'b0),
 123         .Y(y), .X(x), .CO(co),
 124 );
 125 endmodule
 126 EOT
 127
 128 equiv_opt -assert opt
 129 design -load postopt
 130 select -assert-none t:$alu
 131
 132
 133 design -reset
 134 read_verilog -icells <<EOT
 135 module test(input [3:0] a, output [3:0] y, output [3:0] x, output [3:0] co);
 136 $alu #(
 137         .A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
 138         .A_SIGNED(0), .B_SIGNED(0),
 139 ) alu (
 140         .A(a), .B(4'h0),
 141         .BI(1'b1), .CI(1'b1),
 142         .Y(y), .X(x), .CO(co),
 143 );
 144 endmodule
 145 EOT
 146
 147 equiv_opt -assert opt
 148 design -load postopt
 149 select -assert-none t:$alu
 150
 151
 152 design -reset
 153 read_verilog -icells <<EOT
 154 module test(input [3:0] a, output [3:0] y, output [3:0] x, output [3:0] co);
 155 $alu #(
 156         .A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
 157         .A_SIGNED(0), .B_SIGNED(0),
 158 ) alu (
 159         .A(4'h0), .B(a),
 160         .BI(1'b0), .CI(1'b0),
 161         .Y(y), .X(x), .CO(co),
 162 );
 163 endmodule
 164 EOT
 165
 166 equiv_opt -assert opt
 167 design -load postopt
 168 select -assert-none t:$alu