Add ability to override verilog mode for verific -f command
[yosys.git] / tests / opt / opt_expr_cmp.v
1 module top(...);
2 input [3:0] a;
3
4 output o1_1 = 4'b0000 > a;
5 output o1_2 = 4'b0000 <= a;
6 output o1_3 = 4'b1111 < a;
7 output o1_4 = 4'b1111 >= a;
8 output o1_5 = a < 4'b0000;
9 output o1_6 = a >= 4'b0000;
10 output o1_7 = a > 4'b1111;
11 output o1_8 = a <= 4'b1111;
12
13 output o2_1 = 4'sb0000 > $signed(a);
14 output o2_2 = 4'sb0000 <= $signed(a);
15 output o2_3 = $signed(a) < 4'sb0000;
16 output o2_4 = $signed(a) >= 4'sb0000;
17
18 output o3_1 = 4'b0100 > a;
19 output o3_2 = 4'b0100 <= a;
20 output o3_3 = a < 4'b0100;
21 output o3_4 = a >= 4'b0100;
22
23 output o4_1 = 5'b10000 > a;
24 output o4_2 = 5'b10000 >= a;
25 output o4_3 = 5'b10000 < a;
26 output o4_4 = 5'b10000 <= a;
27 output o4_5 = a < 5'b10000;
28 output o4_6 = a <= 5'b10000;
29 output o4_7 = a > 5'b10000;
30 output o4_8 = a >= 5'b10000;
31
32 output o5_1 = 5'b10100 > a;
33 output o5_2 = 5'b10100 >= a;
34 output o5_3 = 5'b10100 < a;
35 output o5_4 = 5'b10100 <= a;
36 output o5_5 = a < 5'b10100;
37 output o5_6 = a <= 5'b10100;
38 output o5_7 = a > 5'b10100;
39 output o5_8 = a >= 5'b10100;
40 endmodule