tests/opt/opt_expr_combined_assign.ys

   1 read_verilog -sv <<EOT
   2 module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o);
   3 wire[8:0] a = 8'b0;
   4 initial begin
   5         a |= i;
   6         a |= j;
   7 end
   8     assign o = a;
   9 endmodule
  10 EOT
  11 proc
  12 equiv_opt -assert opt_expr -fine
  13 design -load postopt
  14
  15 select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
  16
  17 design -reset
  18 read_verilog -sv <<EOT
  19 module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
  20 wire[8:0] a = 8'b0;
  21 initial begin
  22         a += i;
  23         a += j;
  24 end
  25     assign o = a;
  26 endmodule
  27 EOT
  28 proc
  29 equiv_opt -assert opt_expr -fine
  30 design -load postopt
  31
  32 select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
  33
  34 design -reset
  35 read_verilog -sv <<EOT
  36 module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
  37 wire[8:0] a = 8'b0;
  38 initial begin
  39         a ^= i;
  40         a ^= j;
  41 end
  42     assign o = a;
  43 endmodule
  44 EOT
  45 proc
  46 equiv_opt -assert opt_expr -fine
  47 design -load postopt
  48
  49 select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
  50
  51 design -reset
  52 read_verilog -sv <<EOT
  53 module opt_expr_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
  54 wire[8:0] a = 8'b0;
  55 initial begin
  56         a -= i;
  57         a -= j;
  58 end
  59     assign o = a;
  60 endmodule
  61 EOT
  62 proc
  63 equiv_opt -assert opt_expr -fine
  64 design -load postopt
  65
  66 select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
  67
  68 design -reset
  69 read_verilog -sv <<EOT
  70 module opt_expr_and_test(input [3:0] i, input [7:0] j, output [8:0] o);
  71 wire[8:0] a = 8'b11111111;
  72 initial begin
  73         a &= i;
  74         a &= j;
  75 end
  76     assign o = a;
  77 endmodule
  78 EOT
  79 proc
  80 equiv_opt -assert opt_expr -fine
  81 design -load postopt
  82
  83 select -assert-count 1 t:$and r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i