projects
/
yosys.git
/ blob
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
history
|
raw
|
HEAD
Add ability to override verilog mode for verific -f command
[yosys.git]
/
tests
/
opt
/
opt_expr_constconn.v
1
module top(...);
2
3
input [7:0] A;
4
output [7:0] B;
5
wire [7:0] C = 3;
6
assign B = A + C;
7
8
endmodule