tests/opt/opt_ff.v

   1 module top(
   2     input clk,
   3     input rst,
   4     input [2:0] a,
   5     output [1:0] b
   6 );
   7     reg [2:0] b_reg;
   8     initial begin
   9         b_reg <= 3'b0;
  10     end
  11
  12     assign b = b_reg[1:0];
  13     always @(posedge clk or posedge rst) begin
  14         if(rst) begin
  15             b_reg <= 3'b0;
  16         end else begin
  17             b_reg <= a;
  18         end
  19     end
  20 endmodule
  21