proc_arst: Add special-casing of clock signal in conditionals.
[yosys.git] / tests / opt / opt_lut.v
1 module top(
2 input [8:0] a,
3 input [8:0] b,
4 output [8:0] o1,
5 output [2:0] o2,
6 input [2:0] c,
7 input [2:0] d,
8 output [2:0] o3,
9 output [2:0] o4,
10 input s
11 );
12
13 assign o1 = (s ? 0 : a + b);
14 assign o2 = (s ? a : a - b);
15 assign o3 = (s ? 4'b1111 : d + c);
16 assign o4 = (s ? d : c - d);
17
18 endmodule