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Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
[yosys.git] / tests / opt / opt_lut.ys
1 read_verilog opt_lut.v
2 synth_ice40
3 ice40_unlut
4 equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3