tests/opt/opt_lut.ys

   1 read_verilog opt_lut.v
   2 synth_ice40
   3 ice40_unlut
   4 design -save preopt
   5
   6 opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
   7 design -stash postopt
   8
   9 design -copy-from preopt -as preopt top
  10 design -copy-from postopt -as postopt top
  11 equiv_make preopt postopt equiv
  12 techmap -map ice40_carry.v
  13 prep -flatten -top equiv
  14 equiv_induct
  15 equiv_status -assert