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Merge pull request #1143 from YosysHQ/clifford/fix1135
[yosys.git]
/
tests
/
opt
/
opt_lut_elim.il
1
module \test
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wire input 1 \i
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wire output 2 \o1
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cell $lut $1
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parameter \LUT 16'0110100110010110
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parameter \WIDTH 4
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connect \A { \i 3'000 }
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connect \Y \o1
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end
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wire output 2 \o2
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cell $lut $2
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parameter \LUT 16'0110100010010110
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parameter \WIDTH 4
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connect \A { \i 3'000 }
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connect \Y \o2
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end
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end