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Merge pull request #1143 from YosysHQ/clifford/fix1135
[yosys.git]
/
tests
/
opt
/
opt_lut_port.il
1
module $1
2
wire width 4 input 2 \_0_
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wire output 4 \_1_
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wire input 3 \_2_
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wire output 1 \o
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cell $lut \_3_
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parameter \LUT 16'0011000000000011
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parameter \WIDTH 4
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connect \A { \_0_ [3] \o 2'00 }
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connect \Y \_1_
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end
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cell $lut \_4_
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parameter \LUT 4'0001
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parameter \WIDTH 4
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connect \A { 3'000 \_2_ }
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connect \Y \o
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end
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end