1 read_verilog -icells <<EOT
2 module top(input clk, i, (* init = 1'b0 *) output o, p);
23 select -assert-count 1 t:$dff
24 select -assert-count 1 a:init=1'0
28 read_verilog -icells <<EOT
29 module top(input clk, i, (* init = 2'b11 *) output [1:0] o);
50 select -assert-count 1 t:$dff
51 select -assert-count 1 a:init=2'bx1
55 read_verilog -icells <<EOT
56 module top(input clk, i, (* init = 1'b0 *) output o, /* NB: no init here! */ output p);
77 select -assert-count 2 t:$dff