tests/opt/opt_merge_init.ys

   1 read_verilog -icells <<EOT
   2 module top(input clk, i, (* init = 1'b0 *) output o, p);
   3   \$dff  #(
   4     .CLK_POLARITY(1'h1),
   5     .WIDTH(32'd1)
   6   ) ffo  (
   7     .CLK(clk),
   8     .D(i),
   9     .Q(o)
  10   );
  11   \$dff  #(
  12     .CLK_POLARITY(1'h1),
  13     .WIDTH(32'd1)
  14   ) ffp  (
  15     .CLK(clk),
  16     .D(i),
  17     .Q(p)
  18   );
  19 endmodule
  20 EOT
  21
  22 opt_merge
  23 select -assert-count 1 t:$dff
  24 select -assert-count 1 a:init=1'0
  25
  26
  27 design -reset
  28 read_verilog -icells <<EOT
  29 module top(input clk, i, (* init = 2'b11 *) output [1:0] o);
  30   \$dff  #(
  31     .CLK_POLARITY(1'h1),
  32     .WIDTH(32'd1)
  33   ) ff1  (
  34     .CLK(clk),
  35     .D(i),
  36     .Q(o[1])
  37   );
  38   \$dff  #(
  39     .CLK_POLARITY(1'h1),
  40     .WIDTH(32'd1)
  41   ) ff0  (
  42     .CLK(clk),
  43     .D(i),
  44     .Q(o[0])
  45   );
  46 endmodule
  47 EOT
  48
  49 opt_merge
  50 select -assert-count 1 t:$dff
  51 select -assert-count 1 a:init=2'bx1 a:init=2'b1x
  52
  53
  54 design -reset
  55 read_verilog -icells <<EOT
  56 module top(input clk, i, (* init = 1'b0 *) output o, /* NB: no init here! */ output p);
  57   \$dff  #(
  58     .CLK_POLARITY(1'h1),
  59     .WIDTH(32'd1)
  60   ) ffo  (
  61     .CLK(clk),
  62     .D(i),
  63     .Q(o)
  64   );
  65   \$dff  #(
  66     .CLK_POLARITY(1'h1),
  67     .WIDTH(32'd1)
  68   ) ffp  (
  69     .CLK(clk),
  70     .D(i),
  71     .Q(p)
  72   );
  73 endmodule
  74 EOT
  75
  76 opt_merge
  77 select -assert-count 2 t:$dff
  78
  79 design -reset
  80 read_verilog -icells <<EOT
  81 module top(input clk, i, (* init = 1'b0 *) output o, p);
  82   \$dff  #(
  83     .CLK_POLARITY(1'h1),
  84     .WIDTH(32'd1)
  85   ) ffo  (
  86     .CLK(clk),
  87     .D(i),
  88     .Q(o)
  89   );
  90   \$dff  #(
  91     .CLK_POLARITY(1'h1),
  92     .WIDTH(32'd1)
  93   ) ffp  (
  94     .CLK(clk),
  95     .D(i),
  96     .Q(p)
  97   );
  98 endmodule
  99 EOT
 100
 101 opt_merge -keepdc
 102 select -assert-count 1 t:$dff
 103
 104 design -reset
 105 read_verilog -icells <<EOT
 106 module top(input clk, i, output o, p);
 107   \$dff  #(
 108     .CLK_POLARITY(1'h1),
 109     .WIDTH(32'd1)
 110   ) ffo  (
 111     .CLK(clk),
 112     .D(i),
 113     .Q(o)
 114   );
 115   \$dff  #(
 116     .CLK_POLARITY(1'h1),
 117     .WIDTH(32'd1)
 118   ) ffp  (
 119     .CLK(clk),
 120     .D(i),
 121     .Q(p)
 122   );
 123 endmodule
 124 EOT
 125
 126 opt_merge -keepdc
 127 select -assert-count 2 t:$dff