tests/opt/opt_merge_keep.ys

   1 read_verilog -icells <<EOT
   2 module top(input clk, i, output o, p);
   3   (* keep *)
   4   \$_DFF_P_ ffo  (
   5     .C(clk),
   6     .D(i),
   7     .Q(o)
   8   );
   9   \$_DFF_P_ ffp  (
  10     .C(clk),
  11     .D(i),
  12     .Q(p)
  13   );
  14 endmodule
  15 EOT
  16
  17 opt_merge
  18 select -assert-count 1 t:$_DFF_P_
  19 select -assert-count 1 a:keep
  20
  21
  22 design -reset
  23 read_verilog -icells <<EOT
  24 module top(input clk, i, output o, p);
  25   \$_DFF_P_ ffo  (
  26     .C(clk),
  27     .D(i),
  28     .Q(o)
  29   );
  30   (* keep *)
  31   \$_DFF_P_ ffp  (
  32     .C(clk),
  33     .D(i),
  34     .Q(p)
  35   );
  36 endmodule
  37 EOT
  38
  39 opt_merge
  40 select -assert-count 1 t:$_DFF_P_
  41 select -assert-count 1 a:keep
  42
  43
  44 design -reset
  45 read_verilog -icells <<EOT
  46 module top(input clk, i, output o, p);
  47   (* keep *)
  48   \$_DFF_P_ ffo  (
  49     .C(clk),
  50     .D(i),
  51     .Q(o)
  52   );
  53   (* keep *)
  54   \$_DFF_P_ ffp  (
  55     .C(clk),
  56     .D(i),
  57     .Q(p)
  58   );
  59 endmodule
  60 EOT
  61
  62 opt_merge
  63 select -assert-count 2 t:$_DFF_P_
  64 select -assert-count 2 a:keep