tests/opt/opt_reduce_bmux.ys

   1 read_ilang << EOT
   2
   3 module \top
   4   wire width 12 input 0 \A
   5   wire width 2 input 1 \S
   6   wire width 6 output 2 \Y
   7
   8   cell $bmux $0
   9     parameter \WIDTH 6
  10     parameter \S_WIDTH 2
  11     connect \A { \A [11:10] \A [3:2] \A [10:9] \A [7] \A [7] \A [8] \A [2] \A [7:6] \A [5] \A [5] \A [3:2] \A [5:4] \A [1] \A [1] \A [3:0] }
  12     connect \S \S
  13     connect \Y \Y
  14   end
  15 end
  16
  17 EOT
  18
  19 equiv_opt -assert opt_reduce -fine
  20 opt_reduce -fine
  21 select -assert-count 1 t:$bmux r:WIDTH=4 %i
  22
  23 design -reset
  24
  25 read_ilang << EOT
  26
  27 module \top
  28   wire width 6 input 0 \A
  29   wire width 2 input 1 \S
  30   wire width 6 output 2 \Y
  31
  32   cell $bmux $0
  33     parameter \WIDTH 6
  34     parameter \S_WIDTH 2
  35     connect \A { \A [5:0] \A [5:0] \A [5:0] \A [5:0] }
  36     connect \S \S
  37     connect \Y \Y
  38   end
  39 end
  40
  41 EOT
  42
  43 equiv_opt -assert opt_reduce -fine
  44 opt_reduce -fine
  45 select -assert-count 0 t:$bmux
  46
  47 design -reset
  48
  49 read_ilang << EOT
  50
  51 module \top
  52   wire width 160 input 0 \A
  53   wire width 2 input 1 \S
  54   wire width 5 output 2 \Y
  55
  56   cell $bmux $0
  57     parameter \WIDTH 5
  58     parameter \S_WIDTH 5
  59     connect \A \A
  60     connect \S { \S [1] 1'1 \S [0] \S [1] 1'0 }
  61     connect \Y \Y
  62   end
  63 end
  64
  65 EOT
  66
  67 equiv_opt -assert opt_reduce -fine
  68 opt_reduce -fine
  69 select -assert-count 1 t:$bmux r:S_WIDTH=2 %i
  70
  71 design -reset
  72
  73 read_ilang << EOT
  74
  75 module \top
  76   wire width 10 input 0 \A
  77   wire input 1 \S
  78   wire width 5 output 2 \Y
  79
  80   cell $bmux $0
  81     parameter \WIDTH 5
  82     parameter \S_WIDTH 1
  83     connect \A \A
  84     connect \S \S
  85     connect \Y \Y
  86   end
  87 end
  88
  89 EOT
  90
  91 equiv_opt -assert opt_reduce -fine
  92 opt_reduce -fine
  93 select -assert-count 0 t:$bmux
  94 select -assert-count 1 t:$mux
  95
  96 design -reset
  97
  98 read_ilang << EOT
  99
 100 module \top
 101   wire width 5 input 0 \A
 102   wire width 5 output 1 \Y
 103
 104   cell $bmux $0
 105     parameter \WIDTH 5
 106     parameter \S_WIDTH 0
 107     connect \A \A
 108     connect \S { }
 109     connect \Y \Y
 110   end
 111 end
 112
 113 EOT
 114
 115 equiv_opt -assert opt_reduce -fine
 116 opt_reduce -fine
 117 select -assert-count 0 t:$bmux