Add ability to override verilog mode for verific -f command
[yosys.git] / tests / opt / opt_reduce_demux.ys
1 read_ilang << EOT
2
3 module \top
4 wire width 4 input 0 \A
5 wire width 2 input 1 \S
6 wire width 24 output 2 \Y
7
8 cell $demux $0
9 parameter \WIDTH 6
10 parameter \S_WIDTH 2
11 connect \A { \A [3] \A [1] 1'0 \A [2:0] }
12 connect \S \S
13 connect \Y \Y
14 end
15 end
16
17 EOT
18
19 equiv_opt -assert opt_reduce -fine
20 opt_reduce -fine
21 select -assert-count 1 t:$demux r:WIDTH=4 %i
22
23 design -reset
24
25 read_ilang << EOT
26
27 module \top
28 wire width 2 input 1 \S
29 wire width 24 output 2 \Y
30
31 cell $demux $0
32 parameter \WIDTH 6
33 parameter \S_WIDTH 2
34 connect \A 6'000000
35 connect \S \S
36 connect \Y \Y
37 end
38 end
39
40 EOT
41
42 equiv_opt -assert opt_reduce -fine
43 opt_reduce -fine
44 select -assert-count 0 t:$demux
45
46 design -reset
47
48 read_ilang << EOT
49
50 module \top
51 wire width 5 input 0 \A
52 wire width 2 input 1 \S
53 wire width 160 output 2 \Y
54
55 cell $demux $0
56 parameter \WIDTH 5
57 parameter \S_WIDTH 5
58 connect \A \A
59 connect \S { \S [0] \S [1] 1'1 \S [0] 1'0 }
60 connect \Y \Y
61 end
62 end
63
64 EOT
65
66 equiv_opt -assert opt_reduce -fine
67 opt_reduce -fine
68 select -assert-count 1 t:$demux r:S_WIDTH=2 %i
69
70 design -reset
71
72 read_ilang << EOT
73
74 module \top
75 wire width 5 input 0 \A
76 wire width 20 output 2 \Y
77
78 cell $demux $0
79 parameter \WIDTH 5
80 parameter \S_WIDTH 2
81 connect \A \A
82 connect \S { 2'10 }
83 connect \Y \Y
84 end
85 end
86
87 EOT
88
89 equiv_opt -assert opt_reduce -fine
90 opt_reduce -fine
91 select -assert-count 0 t:$demux