tests/opt/opt_rmdff.ys

   1 read_verilog -icells opt_rmdff.v
   2 prep
   3 design -stash gold
   4
   5 read_verilog -icells opt_rmdff.v
   6 proc
   7 opt_dff
   8
   9 select -assert-count 0 c:remove*
  10 select -assert-min 7 c:keep*
  11 select -assert-count 0  t:$dffe 7:$_DFFE_* %u c:noenable* %i
  12
  13 design -stash gate
  14
  15 design -import gold -as gold
  16 design -import gate -as gate
  17
  18 cd gold
  19 # fix up the "EN is don't care" cases, so that the gold output can't
  20 # become defined by using the properties of an undefined enable. (Both
  21 # remove6 and remove15 have active-low enables.)
  22 connect -port remove6 EN 1'b1
  23 connect -port remove15 E 1'b1
  24 cd ..
  25
  26 clk2fflogic
  27 opt_clean
  28
  29 miter -equiv -ignore_gold_x -make_assert -make_outputs -make_outcmp -flatten gold gate miter
  30 hierarchy -top miter
  31
  32 sat -verify -prove-asserts -enable_undef -set-init-undef -seq 10 -show-public miter