tests/opt/opt_share_bug2334.ys

   1 read_verilog <<EOT
   2
   3 module t(input [3:0] A, input [3:0] B, input [3:0] C, input S, output [3:0] Y);
   4
   5 wire [3:0] t = A + C;
   6
   7 assign Y = S ? A + B : {4{t[0]}};
   8
   9 endmodule
  10
  11 EOT
  12
  13 equiv_opt -assert opt_share