tests/opt/opt_share_bug2538.ys

   1 read_verilog <<EOT
   2
   3 module top(...);
   4
   5 input [3:0] A;
   6 input S;
   7 output [1:0] Y;
   8
   9 wire [3:0] A1 = A + 1;
  10 wire [3:0] A2 = A + 2;
  11 assign Y = S ? A1[3:2] : A2[3:2];
  12
  13 endmodule
  14
  15 EOT
  16
  17 proc
  18 alumacc
  19 equiv_opt -assert opt_share
  20