Add ability to override verilog mode for verific -f command
[yosys.git] / tests / opt / opt_share_cat.v
1 module opt_share_test(
2 input [15:0] a,
3 input [15:0] b,
4 input [15:0] c,
5 input [15:0] d,
6 input sel,
7 output [63:0] res,
8 );
9
10 reg [31: 0] cat1 = {a+b, c+d};
11 reg [31: 0] cat2 = {a-b, c-d};
12
13 assign res = {b, sel ? cat1 : cat2, a};
14
15 endmodule