proc_arst: Add special-casing of clock signal in conditionals.
[yosys.git] / tests / opt / opt_share_cat_multiuser.ys
1 read_verilog opt_share_cat_multiuser.v
2 proc;;
3 copy opt_share_test merged
4
5 alumacc merged
6 opt merged
7 opt_share merged
8 opt_clean merged
9
10 miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
11 sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
12
13 select -assert-count 3 -module merged t:$alu