1 read_verilog opt_share_cat_multiuser.v
3 copy opt_share_test merged
10 miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
11 sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
13 select -assert-count 3 -module merged t:$alu