tests/opt/opt_share_diff_port_widths.v

   1 module opt_share_test(
   2   input [15:0]       a,
   3   input [15:0]       b,
   4   input [15:0]       c,
   5   input [1:0]      sel,
   6   output reg [15:0] res
   7   );
   8
   9   wire [15:0]       add0_res = a+b;
  10   wire [15:0]       add1_res = a+c;
  11
  12   always @* begin
  13     case(sel)
  14       0: res = add0_res[10:0];
  15       1: res = add1_res[10:0];
  16       2: res = a - b;
  17       default: res = 32'bx;
  18     endcase
  19   end
  20
  21 endmodule