Update reference config.ini files to include port mappings.
[gem5.git] / tests / quick / 00.hello / ref / alpha / linux / simple-timing / config.ini
1 [root]
2 type=Root
3 children=system
4 checkpoint=
5 clock=1000000000000
6 max_tick=0
7 output_file=cout
8 progress_interval=0
9
10 [debug]
11 break_cycles=
12
13 [exetrace]
14 intel_format=false
15 pc_symbol=true
16 print_cpseq=false
17 print_cycle=true
18 print_data=true
19 print_effaddr=true
20 print_fetchseq=false
21 print_iregs=false
22 print_opclass=true
23 print_thread=true
24 speculative=true
25 trace_system=client
26
27 [serialize]
28 count=10
29 cycle=0
30 dir=cpt.%012d
31 period=0
32
33 [stats]
34 descriptions=true
35 dump_cycle=0
36 dump_period=0
37 dump_reset=false
38 ignore_events=
39 mysql_db=
40 mysql_host=
41 mysql_password=
42 mysql_user=
43 project_name=test
44 simulation_name=test
45 simulation_sample=0
46 text_compat=true
47 text_file=m5stats.txt
48
49 [system]
50 type=System
51 children=cpu membus physmem
52 mem_mode=atomic
53 physmem=system.physmem
54
55 [system.cpu]
56 type=TimingSimpleCPU
57 children=dcache icache l2cache toL2Bus workload
58 clock=1
59 defer_registration=false
60 function_trace=false
61 function_trace_start=0
62 max_insts_all_threads=0
63 max_insts_any_thread=0
64 max_loads_all_threads=0
65 max_loads_any_thread=0
66 mem=system.cpu.dcache
67 system=system
68 workload=system.cpu.workload
69 dcache_port=system.cpu.dcache.cpu_side
70 icache_port=system.cpu.icache.cpu_side
71
72 [system.cpu.dcache]
73 type=BaseCache
74 adaptive_compression=false
75 assoc=2
76 block_size=64
77 compressed_bus=false
78 compression_latency=0
79 do_copy=false
80 hash_delay=1
81 hit_latency=1
82 latency=1
83 lifo=false
84 max_miss_count=0
85 mshrs=10
86 prefetch_access=false
87 prefetch_cache_check_push=true
88 prefetch_data_accesses_only=false
89 prefetch_degree=1
90 prefetch_latency=10
91 prefetch_miss=false
92 prefetch_past_page=false
93 prefetch_policy=none
94 prefetch_serial_squash=false
95 prefetch_use_cpu_id=true
96 prefetcher_size=100
97 prioritizeRequests=false
98 protocol=Null
99 repl=Null
100 size=262144
101 split=false
102 split_size=0
103 store_compressed=false
104 subblock_size=0
105 tgts_per_mshr=5
106 trace_addr=0
107 two_queue=false
108 write_buffers=8
109 cpu_side=system.cpu.dcache_port
110 mem_side=system.cpu.toL2Bus.port[1]
111
112 [system.cpu.icache]
113 type=BaseCache
114 adaptive_compression=false
115 assoc=2
116 block_size=64
117 compressed_bus=false
118 compression_latency=0
119 do_copy=false
120 hash_delay=1
121 hit_latency=1
122 latency=1
123 lifo=false
124 max_miss_count=0
125 mshrs=10
126 prefetch_access=false
127 prefetch_cache_check_push=true
128 prefetch_data_accesses_only=false
129 prefetch_degree=1
130 prefetch_latency=10
131 prefetch_miss=false
132 prefetch_past_page=false
133 prefetch_policy=none
134 prefetch_serial_squash=false
135 prefetch_use_cpu_id=true
136 prefetcher_size=100
137 prioritizeRequests=false
138 protocol=Null
139 repl=Null
140 size=131072
141 split=false
142 split_size=0
143 store_compressed=false
144 subblock_size=0
145 tgts_per_mshr=5
146 trace_addr=0
147 two_queue=false
148 write_buffers=8
149 cpu_side=system.cpu.icache_port
150 mem_side=system.cpu.toL2Bus.port[0]
151
152 [system.cpu.l2cache]
153 type=BaseCache
154 adaptive_compression=false
155 assoc=2
156 block_size=64
157 compressed_bus=false
158 compression_latency=0
159 do_copy=false
160 hash_delay=1
161 hit_latency=1
162 latency=1
163 lifo=false
164 max_miss_count=0
165 mshrs=10
166 prefetch_access=false
167 prefetch_cache_check_push=true
168 prefetch_data_accesses_only=false
169 prefetch_degree=1
170 prefetch_latency=10
171 prefetch_miss=false
172 prefetch_past_page=false
173 prefetch_policy=none
174 prefetch_serial_squash=false
175 prefetch_use_cpu_id=true
176 prefetcher_size=100
177 prioritizeRequests=false
178 protocol=Null
179 repl=Null
180 size=2097152
181 split=false
182 split_size=0
183 store_compressed=false
184 subblock_size=0
185 tgts_per_mshr=5
186 trace_addr=0
187 two_queue=false
188 write_buffers=8
189 cpu_side=system.cpu.toL2Bus.port[2]
190 mem_side=system.membus.port[1]
191
192 [system.cpu.toL2Bus]
193 type=Bus
194 bus_id=0
195 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
196
197 [system.cpu.workload]
198 type=LiveProcess
199 cmd=hello
200 env=
201 executable=tests/test-progs/hello/bin/alpha/linux/hello
202 input=cin
203 output=cout
204 system=system
205
206 [system.membus]
207 type=Bus
208 bus_id=0
209 port=system.physmem.port system.cpu.l2cache.mem_side
210
211 [system.physmem]
212 type=PhysicalMemory
213 file=
214 latency=1
215 range=0:134217727
216 port=system.membus.port[0]
217
218 [trace]
219 bufsize=0
220 dump_on_exit=false
221 file=cout
222 flags=
223 ignore=
224 start=0
225