Updates refs.
[gem5.git] / tests / quick / 00.hello / ref / alpha / linux / simple-timing / config.ini
1 [root]
2 type=Root
3 children=system
4 checkpoint=
5 clock=1000000000000
6 max_tick=0
7 output_file=cout
8 progress_interval=0
9
10 [debug]
11 break_cycles=
12
13 [exetrace]
14 intel_format=false
15 pc_symbol=true
16 print_cpseq=false
17 print_cycle=true
18 print_data=true
19 print_effaddr=true
20 print_fetchseq=false
21 print_iregs=false
22 print_opclass=true
23 print_thread=true
24 speculative=true
25 trace_system=client
26
27 [serialize]
28 count=10
29 cycle=0
30 dir=cpt.%012d
31 period=0
32
33 [stats]
34 descriptions=true
35 dump_cycle=0
36 dump_period=0
37 dump_reset=false
38 ignore_events=
39 mysql_db=
40 mysql_host=
41 mysql_password=
42 mysql_user=
43 project_name=test
44 simulation_name=test
45 simulation_sample=0
46 text_compat=true
47 text_file=m5stats.txt
48
49 [system]
50 type=System
51 children=cpu membus physmem
52 mem_mode=atomic
53 physmem=system.physmem
54
55 [system.cpu]
56 type=TimingSimpleCPU
57 children=dcache icache l2cache toL2Bus workload
58 clock=1
59 cpu_id=0
60 defer_registration=false
61 function_trace=false
62 function_trace_start=0
63 max_insts_all_threads=0
64 max_insts_any_thread=0
65 max_loads_all_threads=0
66 max_loads_any_thread=0
67 mem=system.cpu.dcache
68 progress_interval=0
69 system=system
70 workload=system.cpu.workload
71 dcache_port=system.cpu.dcache.cpu_side
72 icache_port=system.cpu.icache.cpu_side
73
74 [system.cpu.dcache]
75 type=BaseCache
76 adaptive_compression=false
77 assoc=2
78 block_size=64
79 compressed_bus=false
80 compression_latency=0
81 do_copy=false
82 hash_delay=1
83 hit_latency=1
84 latency=1
85 lifo=false
86 max_miss_count=0
87 mshrs=10
88 prefetch_access=false
89 prefetch_cache_check_push=true
90 prefetch_data_accesses_only=false
91 prefetch_degree=1
92 prefetch_latency=10
93 prefetch_miss=false
94 prefetch_past_page=false
95 prefetch_policy=none
96 prefetch_serial_squash=false
97 prefetch_use_cpu_id=true
98 prefetcher_size=100
99 prioritizeRequests=false
100 protocol=Null
101 repl=Null
102 size=262144
103 split=false
104 split_size=0
105 store_compressed=false
106 subblock_size=0
107 tgts_per_mshr=5
108 trace_addr=0
109 two_queue=false
110 write_buffers=8
111 cpu_side=system.cpu.dcache_port
112 mem_side=system.cpu.toL2Bus.port[1]
113
114 [system.cpu.icache]
115 type=BaseCache
116 adaptive_compression=false
117 assoc=2
118 block_size=64
119 compressed_bus=false
120 compression_latency=0
121 do_copy=false
122 hash_delay=1
123 hit_latency=1
124 latency=1
125 lifo=false
126 max_miss_count=0
127 mshrs=10
128 prefetch_access=false
129 prefetch_cache_check_push=true
130 prefetch_data_accesses_only=false
131 prefetch_degree=1
132 prefetch_latency=10
133 prefetch_miss=false
134 prefetch_past_page=false
135 prefetch_policy=none
136 prefetch_serial_squash=false
137 prefetch_use_cpu_id=true
138 prefetcher_size=100
139 prioritizeRequests=false
140 protocol=Null
141 repl=Null
142 size=131072
143 split=false
144 split_size=0
145 store_compressed=false
146 subblock_size=0
147 tgts_per_mshr=5
148 trace_addr=0
149 two_queue=false
150 write_buffers=8
151 cpu_side=system.cpu.icache_port
152 mem_side=system.cpu.toL2Bus.port[0]
153
154 [system.cpu.l2cache]
155 type=BaseCache
156 adaptive_compression=false
157 assoc=2
158 block_size=64
159 compressed_bus=false
160 compression_latency=0
161 do_copy=false
162 hash_delay=1
163 hit_latency=1
164 latency=1
165 lifo=false
166 max_miss_count=0
167 mshrs=10
168 prefetch_access=false
169 prefetch_cache_check_push=true
170 prefetch_data_accesses_only=false
171 prefetch_degree=1
172 prefetch_latency=10
173 prefetch_miss=false
174 prefetch_past_page=false
175 prefetch_policy=none
176 prefetch_serial_squash=false
177 prefetch_use_cpu_id=true
178 prefetcher_size=100
179 prioritizeRequests=false
180 protocol=Null
181 repl=Null
182 size=2097152
183 split=false
184 split_size=0
185 store_compressed=false
186 subblock_size=0
187 tgts_per_mshr=5
188 trace_addr=0
189 two_queue=false
190 write_buffers=8
191 cpu_side=system.cpu.toL2Bus.port[2]
192 mem_side=system.membus.port[1]
193
194 [system.cpu.toL2Bus]
195 type=Bus
196 bus_id=0
197 clock=1000
198 width=64
199 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
200
201 [system.cpu.workload]
202 type=LiveProcess
203 cmd=hello
204 egid=100
205 env=
206 euid=100
207 executable=tests/test-progs/hello/bin/alpha/linux/hello
208 gid=100
209 input=cin
210 output=cout
211 pid=100
212 ppid=99
213 system=system
214 uid=100
215
216 [system.membus]
217 type=Bus
218 bus_id=0
219 clock=1000
220 width=64
221 port=system.physmem.port system.cpu.l2cache.mem_side
222
223 [system.physmem]
224 type=PhysicalMemory
225 file=
226 latency=1
227 range=0:134217727
228 port=system.membus.port[0]
229
230 [trace]
231 bufsize=0
232 cycle=0
233 dump_on_exit=false
234 file=cout
235 flags=
236 ignore=
237 start=0
238