2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 11324 # Simulator instruction rate (inst/s)
4 host_mem_usage 193960 # Number of bytes of host memory used
5 host_seconds 0.50 # Real time elapsed on the host
6 host_tick_rate 38693743 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 5641 # Number of instructions simulated
9 sim_seconds 0.000019 # Number of seconds simulated
10 sim_ticks 19285000 # Number of ticks simulated
11 system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses)
12 system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
13 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
14 system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits
15 system.cpu.dcache.ReadReq_miss_latency 2484000 # number of ReadReq miss cycles
16 system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses
17 system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses
18 system.cpu.dcache.ReadReq_mshr_miss_latency 2208000 # number of ReadReq MSHR miss cycles
19 system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses
20 system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses
21 system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
22 system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
23 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
24 system.cpu.dcache.WriteReq_hits 725 # number of WriteReq hits
25 system.cpu.dcache.WriteReq_miss_latency 2349000 # number of WriteReq miss cycles
26 system.cpu.dcache.WriteReq_miss_rate 0.107143 # miss rate for WriteReq accesses
27 system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
28 system.cpu.dcache.WriteReq_mshr_miss_latency 2088000 # number of WriteReq MSHR miss cycles
29 system.cpu.dcache.WriteReq_mshr_miss_rate 0.107143 # mshr miss rate for WriteReq accesses
30 system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
31 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
32 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
33 system.cpu.dcache.avg_refs 9.854545 # Average number of references to valid blocks.
34 system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
35 system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
36 system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
37 system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
38 system.cpu.dcache.cache_copies 0 # number of cache copies performed
39 system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses
40 system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
41 system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
42 system.cpu.dcache.demand_hits 1612 # number of demand (read+write) hits
43 system.cpu.dcache.demand_miss_latency 4833000 # number of demand (read+write) miss cycles
44 system.cpu.dcache.demand_miss_rate 0.099944 # miss rate for demand accesses
45 system.cpu.dcache.demand_misses 179 # number of demand (read+write) misses
46 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
47 system.cpu.dcache.demand_mshr_miss_latency 4296000 # number of demand (read+write) MSHR miss cycles
48 system.cpu.dcache.demand_mshr_miss_rate 0.099944 # mshr miss rate for demand accesses
49 system.cpu.dcache.demand_mshr_misses 179 # number of demand (read+write) MSHR misses
50 system.cpu.dcache.fast_writes 0 # number of fast writes performed
51 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
52 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
53 system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses
54 system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
55 system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
56 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
57 system.cpu.dcache.overall_hits 1612 # number of overall hits
58 system.cpu.dcache.overall_miss_latency 4833000 # number of overall miss cycles
59 system.cpu.dcache.overall_miss_rate 0.099944 # miss rate for overall accesses
60 system.cpu.dcache.overall_misses 179 # number of overall misses
61 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
62 system.cpu.dcache.overall_mshr_miss_latency 4296000 # number of overall MSHR miss cycles
63 system.cpu.dcache.overall_mshr_miss_rate 0.099944 # mshr miss rate for overall accesses
64 system.cpu.dcache.overall_mshr_misses 179 # number of overall MSHR misses
65 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
66 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
67 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
68 system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
69 system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
70 system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
71 system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
72 system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
73 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
74 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
75 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
76 system.cpu.dcache.replacements 0 # number of replacements
77 system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks.
78 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
79 system.cpu.dcache.tagsinuse 102.207107 # Cycle average of tags in use
80 system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks.
81 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
82 system.cpu.dcache.writebacks 0 # number of writebacks
83 system.cpu.dtb.accesses 1801 # DTB accesses
84 system.cpu.dtb.acv 0 # DTB access violations
85 system.cpu.dtb.hits 1791 # DTB hits
86 system.cpu.dtb.misses 10 # DTB misses
87 system.cpu.dtb.read_accesses 986 # DTB read accesses
88 system.cpu.dtb.read_acv 0 # DTB read access violations
89 system.cpu.dtb.read_hits 979 # DTB read hits
90 system.cpu.dtb.read_misses 7 # DTB read misses
91 system.cpu.dtb.write_accesses 815 # DTB write accesses
92 system.cpu.dtb.write_acv 0 # DTB write access violations
93 system.cpu.dtb.write_hits 812 # DTB write hits
94 system.cpu.dtb.write_misses 3 # DTB write misses
95 system.cpu.icache.ReadReq_accesses 5652 # number of ReadReq accesses(hits+misses)
96 system.cpu.icache.ReadReq_avg_miss_latency 26953.068592 # average ReadReq miss latency
97 system.cpu.icache.ReadReq_avg_mshr_miss_latency 23953.068592 # average ReadReq mshr miss latency
98 system.cpu.icache.ReadReq_hits 5375 # number of ReadReq hits
99 system.cpu.icache.ReadReq_miss_latency 7466000 # number of ReadReq miss cycles
100 system.cpu.icache.ReadReq_miss_rate 0.049009 # miss rate for ReadReq accesses
101 system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses
102 system.cpu.icache.ReadReq_mshr_miss_latency 6635000 # number of ReadReq MSHR miss cycles
103 system.cpu.icache.ReadReq_mshr_miss_rate 0.049009 # mshr miss rate for ReadReq accesses
104 system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses
105 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
106 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
107 system.cpu.icache.avg_refs 19.404332 # Average number of references to valid blocks.
108 system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
109 system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
110 system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
111 system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
112 system.cpu.icache.cache_copies 0 # number of cache copies performed
113 system.cpu.icache.demand_accesses 5652 # number of demand (read+write) accesses
114 system.cpu.icache.demand_avg_miss_latency 26953.068592 # average overall miss latency
115 system.cpu.icache.demand_avg_mshr_miss_latency 23953.068592 # average overall mshr miss latency
116 system.cpu.icache.demand_hits 5375 # number of demand (read+write) hits
117 system.cpu.icache.demand_miss_latency 7466000 # number of demand (read+write) miss cycles
118 system.cpu.icache.demand_miss_rate 0.049009 # miss rate for demand accesses
119 system.cpu.icache.demand_misses 277 # number of demand (read+write) misses
120 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
121 system.cpu.icache.demand_mshr_miss_latency 6635000 # number of demand (read+write) MSHR miss cycles
122 system.cpu.icache.demand_mshr_miss_rate 0.049009 # mshr miss rate for demand accesses
123 system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses
124 system.cpu.icache.fast_writes 0 # number of fast writes performed
125 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
126 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
127 system.cpu.icache.overall_accesses 5652 # number of overall (read+write) accesses
128 system.cpu.icache.overall_avg_miss_latency 26953.068592 # average overall miss latency
129 system.cpu.icache.overall_avg_mshr_miss_latency 23953.068592 # average overall mshr miss latency
130 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
131 system.cpu.icache.overall_hits 5375 # number of overall hits
132 system.cpu.icache.overall_miss_latency 7466000 # number of overall miss cycles
133 system.cpu.icache.overall_miss_rate 0.049009 # miss rate for overall accesses
134 system.cpu.icache.overall_misses 277 # number of overall misses
135 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
136 system.cpu.icache.overall_mshr_miss_latency 6635000 # number of overall MSHR miss cycles
137 system.cpu.icache.overall_mshr_miss_rate 0.049009 # mshr miss rate for overall accesses
138 system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses
139 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
140 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
141 system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
142 system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
143 system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
144 system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
145 system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
146 system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
147 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
148 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
149 system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
150 system.cpu.icache.replacements 0 # number of replacements
151 system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks.
152 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
153 system.cpu.icache.tagsinuse 127.893604 # Cycle average of tags in use
154 system.cpu.icache.total_refs 5375 # Total number of references to valid blocks.
155 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
156 system.cpu.icache.writebacks 0 # number of writebacks
157 system.cpu.idle_fraction 0 # Percentage of idle cycles
158 system.cpu.itb.accesses 5669 # ITB accesses
159 system.cpu.itb.acv 0 # ITB acv
160 system.cpu.itb.hits 5652 # ITB hits
161 system.cpu.itb.misses 17 # ITB misses
162 system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
163 system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
164 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
165 system.cpu.l2cache.ReadExReq_miss_latency 1679000 # number of ReadExReq miss cycles
166 system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
167 system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
168 system.cpu.l2cache.ReadExReq_mshr_miss_latency 803000 # number of ReadExReq MSHR miss cycles
169 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
170 system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
171 system.cpu.l2cache.ReadReq_accesses 369 # number of ReadReq accesses(hits+misses)
172 system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
173 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
174 system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
175 system.cpu.l2cache.ReadReq_miss_latency 8464000 # number of ReadReq miss cycles
176 system.cpu.l2cache.ReadReq_miss_rate 0.997290 # miss rate for ReadReq accesses
177 system.cpu.l2cache.ReadReq_misses 368 # number of ReadReq misses
178 system.cpu.l2cache.ReadReq_mshr_miss_latency 4048000 # number of ReadReq MSHR miss cycles
179 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997290 # mshr miss rate for ReadReq accesses
180 system.cpu.l2cache.ReadReq_mshr_misses 368 # number of ReadReq MSHR misses
181 system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
182 system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
183 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
184 system.cpu.l2cache.UpgradeReq_miss_latency 322000 # number of UpgradeReq miss cycles
185 system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
186 system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
187 system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles
188 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
189 system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
190 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
191 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
192 system.cpu.l2cache.avg_refs 0.002825 # Average number of references to valid blocks.
193 system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
194 system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
195 system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
196 system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
197 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
198 system.cpu.l2cache.demand_accesses 442 # number of demand (read+write) accesses
199 system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
200 system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
201 system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
202 system.cpu.l2cache.demand_miss_latency 10143000 # number of demand (read+write) miss cycles
203 system.cpu.l2cache.demand_miss_rate 0.997738 # miss rate for demand accesses
204 system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses
205 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
206 system.cpu.l2cache.demand_mshr_miss_latency 4851000 # number of demand (read+write) MSHR miss cycles
207 system.cpu.l2cache.demand_mshr_miss_rate 0.997738 # mshr miss rate for demand accesses
208 system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses
209 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
210 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
211 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
212 system.cpu.l2cache.overall_accesses 442 # number of overall (read+write) accesses
213 system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
214 system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
215 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
216 system.cpu.l2cache.overall_hits 1 # number of overall hits
217 system.cpu.l2cache.overall_miss_latency 10143000 # number of overall miss cycles
218 system.cpu.l2cache.overall_miss_rate 0.997738 # miss rate for overall accesses
219 system.cpu.l2cache.overall_misses 441 # number of overall misses
220 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
221 system.cpu.l2cache.overall_mshr_miss_latency 4851000 # number of overall MSHR miss cycles
222 system.cpu.l2cache.overall_mshr_miss_rate 0.997738 # mshr miss rate for overall accesses
223 system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses
224 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
225 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
226 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
227 system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
228 system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
229 system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
230 system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
231 system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
232 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
233 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
234 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
235 system.cpu.l2cache.replacements 0 # number of replacements
236 system.cpu.l2cache.sampled_refs 354 # Sample count of references to valid blocks.
237 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
238 system.cpu.l2cache.tagsinuse 177.260989 # Cycle average of tags in use
239 system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
240 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
241 system.cpu.l2cache.writebacks 0 # number of writebacks
242 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
243 system.cpu.numCycles 38570 # number of cpu cycles simulated
244 system.cpu.num_insts 5641 # Number of instructions executed
245 system.cpu.num_refs 1801 # Number of memory references
246 system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
248 ---------- End Simulation Statistics ----------
projects / gem5.git / blob