regress: Regression Tester output updates
[gem5.git] / tests / quick / 00.hello / ref / alpha / linux / simple-timing-ruby-MOESI_CMP_token / stats.txt
1
2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 49047 # Simulator instruction rate (inst/s)
4 host_mem_usage 215548 # Number of bytes of host memory used
5 host_seconds 0.13 # Real time elapsed on the host
6 host_tick_rate 1859468 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000 # Frequency of simulated ticks
8 sim_insts 6404 # Number of instructions simulated
9 sim_seconds 0.000243 # Number of seconds simulated
10 sim_ticks 243131 # Number of ticks simulated
11 system.cpu.dtb.data_accesses 2060 # DTB accesses
12 system.cpu.dtb.data_acv 0 # DTB access violations
13 system.cpu.dtb.data_hits 2050 # DTB hits
14 system.cpu.dtb.data_misses 10 # DTB misses
15 system.cpu.dtb.fetch_accesses 0 # ITB accesses
16 system.cpu.dtb.fetch_acv 0 # ITB acv
17 system.cpu.dtb.fetch_hits 0 # ITB hits
18 system.cpu.dtb.fetch_misses 0 # ITB misses
19 system.cpu.dtb.read_accesses 1192 # DTB read accesses
20 system.cpu.dtb.read_acv 0 # DTB read access violations
21 system.cpu.dtb.read_hits 1185 # DTB read hits
22 system.cpu.dtb.read_misses 7 # DTB read misses
23 system.cpu.dtb.write_accesses 868 # DTB write accesses
24 system.cpu.dtb.write_acv 0 # DTB write access violations
25 system.cpu.dtb.write_hits 865 # DTB write hits
26 system.cpu.dtb.write_misses 3 # DTB write misses
27 system.cpu.idle_fraction 0 # Percentage of idle cycles
28 system.cpu.itb.data_accesses 0 # DTB accesses
29 system.cpu.itb.data_acv 0 # DTB access violations
30 system.cpu.itb.data_hits 0 # DTB hits
31 system.cpu.itb.data_misses 0 # DTB misses
32 system.cpu.itb.fetch_accesses 6432 # ITB accesses
33 system.cpu.itb.fetch_acv 0 # ITB acv
34 system.cpu.itb.fetch_hits 6415 # ITB hits
35 system.cpu.itb.fetch_misses 17 # ITB misses
36 system.cpu.itb.read_accesses 0 # DTB read accesses
37 system.cpu.itb.read_acv 0 # DTB read access violations
38 system.cpu.itb.read_hits 0 # DTB read hits
39 system.cpu.itb.read_misses 0 # DTB read misses
40 system.cpu.itb.write_accesses 0 # DTB write accesses
41 system.cpu.itb.write_acv 0 # DTB write access violations
42 system.cpu.itb.write_hits 0 # DTB write hits
43 system.cpu.itb.write_misses 0 # DTB write misses
44 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
45 system.cpu.numCycles 243131 # number of cpu cycles simulated
46 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
47 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
48 system.cpu.num_busy_cycles 243131 # Number of busy cycles
49 system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
50 system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
51 system.cpu.num_fp_insts 10 # number of float instructions
52 system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
53 system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
54 system.cpu.num_func_calls 251 # number of times a function call or return occured
55 system.cpu.num_idle_cycles 0 # Number of idle cycles
56 system.cpu.num_insts 6404 # Number of instructions executed
57 system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
58 system.cpu.num_int_insts 6331 # number of integer instructions
59 system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
60 system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
61 system.cpu.num_load_insts 1192 # Number of load instructions
62 system.cpu.num_mem_refs 2060 # number of memory refs
63 system.cpu.num_store_insts 868 # Number of store instructions
64 system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
65
66 ---------- End Simulation Statistics ----------