2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 0.000018 # Number of seconds simulated
4 sim_ticks 18201500 # Number of ticks simulated
5 final_tick 18201500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 29731 # Simulator instruction rate (inst/s)
8 host_tick_rate 101330259 # Simulator tick rate (ticks/s)
9 host_mem_usage 213072 # Number of bytes of host memory used
10 host_seconds 0.18 # Real time elapsed on the host
11 sim_insts 5340 # Number of instructions simulated
12 system.physmem.bytes_read 27072 # Number of bytes read from this memory
13 system.physmem.bytes_inst_read 18496 # Number of instructions bytes read from this memory
14 system.physmem.bytes_written 0 # Number of bytes written to this memory
15 system.physmem.num_reads 423 # Number of read requests responded to by this memory
16 system.physmem.num_writes 0 # Number of write requests responded to by this memory
17 system.physmem.num_other 0 # Number of other requests responded to by this memory
18 system.physmem.bw_read 1487349944 # Total read bandwidth from this memory (bytes/s)
19 system.physmem.bw_inst_read 1016179985 # Instruction read bandwidth from this memory (bytes/s)
20 system.physmem.bw_total 1487349944 # Total bandwidth to/from this memory (bytes/s)
21 system.cpu.workload.num_syscalls 11 # Number of system calls
22 system.cpu.numCycles 36404 # number of cpu cycles simulated
23 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
24 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
25 system.cpu.contextSwitches 1 # Number of context switches
26 system.cpu.threadCycles 9720 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
27 system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
28 system.cpu.timesIdled 421 # Number of times that the entire CPU went into an idle state and unscheduled itself
29 system.cpu.idleCycles 30130 # Number of cycles cpu's stages were not processed
30 system.cpu.runCycles 6274 # Number of cycles cpu stages are processed.
31 system.cpu.activity 17.234370 # Percentage of cycles cpu is active
32 system.cpu.comLoads 716 # Number of Load instructions committed
33 system.cpu.comStores 673 # Number of Store instructions committed
34 system.cpu.comBranches 1116 # Number of Branches instructions committed
35 system.cpu.comNops 173 # Number of Nop instructions committed
36 system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed
37 system.cpu.comInts 2537 # Number of Integer instructions committed
38 system.cpu.comFloats 0 # Number of Floating Point instructions committed
39 system.cpu.committedInsts 5340 # Number of Instructions Simulated (Per-Thread)
40 system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
41 system.cpu.committedInsts_total 5340 # Number of Instructions Simulated (Total)
42 system.cpu.cpi 6.817228 # CPI: Cycles Per Instruction (Per-Thread)
43 system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
44 system.cpu.cpi_total 6.817228 # CPI: Total CPI of All Threads
45 system.cpu.ipc 0.146687 # IPC: Instructions Per Cycle (Per-Thread)
46 system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
47 system.cpu.ipc_total 0.146687 # IPC: Total IPC of All Threads
48 system.cpu.branch_predictor.lookups 1662 # Number of BP lookups
49 system.cpu.branch_predictor.condPredicted 1123 # Number of conditional branches predicted
50 system.cpu.branch_predictor.condIncorrect 899 # Number of conditional branches incorrect
51 system.cpu.branch_predictor.BTBLookups 1455 # Number of BTB lookups
52 system.cpu.branch_predictor.BTBHits 643 # Number of BTB hits
53 system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target.
54 system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions.
55 system.cpu.branch_predictor.BTBHitPct 44.192440 # BTB Hit Percentage
56 system.cpu.branch_predictor.predictedTaken 710 # Number of Branches Predicted As Taken (True).
57 system.cpu.branch_predictor.predictedNotTaken 952 # Number of Branches Predicted As Not Taken (False).
58 system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File
59 system.cpu.regfile_manager.intRegFileWrites 4000 # Number of Writes to Int. Register File
60 system.cpu.regfile_manager.intRegFileAccesses 9612 # Total Accesses (Read+Write) to the Int. Register File
61 system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
62 system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
63 system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
64 system.cpu.regfile_manager.regForwards 1747 # Number of Registers Read Through Forwarding Logic
65 system.cpu.agen_unit.agens 1473 # Number of Address Generations
66 system.cpu.execution_unit.predictedTakenIncorrect 394 # Number of Branches Incorrectly Predicted As Taken.
67 system.cpu.execution_unit.predictedNotTakenIncorrect 442 # Number of Branches Incorrectly Predicted As Not Taken).
68 system.cpu.execution_unit.mispredicted 836 # Number of Branches Incorrectly Predicted
69 system.cpu.execution_unit.predicted 280 # Number of Branches Incorrectly Predicted
70 system.cpu.execution_unit.mispredictPct 74.910394 # Percentage of Incorrect Branches Predicts
71 system.cpu.execution_unit.executions 3977 # Number of Instructions Executed.
72 system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
73 system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
74 system.cpu.stage0.idleCycles 31738 # Number of cycles 0 instructions are processed.
75 system.cpu.stage0.runCycles 4666 # Number of cycles 1+ instructions are processed.
76 system.cpu.stage0.utilization 12.817273 # Percentage of cycles stage was utilized (processing insts).
77 system.cpu.stage1.idleCycles 33193 # Number of cycles 0 instructions are processed.
78 system.cpu.stage1.runCycles 3211 # Number of cycles 1+ instructions are processed.
79 system.cpu.stage1.utilization 8.820459 # Percentage of cycles stage was utilized (processing insts).
80 system.cpu.stage2.idleCycles 33357 # Number of cycles 0 instructions are processed.
81 system.cpu.stage2.runCycles 3047 # Number of cycles 1+ instructions are processed.
82 system.cpu.stage2.utilization 8.369959 # Percentage of cycles stage was utilized (processing insts).
83 system.cpu.stage3.idleCycles 35421 # Number of cycles 0 instructions are processed.
84 system.cpu.stage3.runCycles 983 # Number of cycles 1+ instructions are processed.
85 system.cpu.stage3.utilization 2.700253 # Percentage of cycles stage was utilized (processing insts).
86 system.cpu.stage4.idleCycles 33233 # Number of cycles 0 instructions are processed.
87 system.cpu.stage4.runCycles 3171 # Number of cycles 1+ instructions are processed.
88 system.cpu.stage4.utilization 8.710581 # Percentage of cycles stage was utilized (processing insts).
89 system.cpu.icache.replacements 0 # number of replacements
90 system.cpu.icache.tagsinuse 136.669321 # Cycle average of tags in use
91 system.cpu.icache.total_refs 791 # Total number of references to valid blocks.
92 system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
93 system.cpu.icache.avg_refs 2.718213 # Average number of references to valid blocks.
94 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
95 system.cpu.icache.occ_blocks::0 136.669321 # Average occupied blocks per context
96 system.cpu.icache.occ_percent::0 0.066733 # Average percentage of cache occupancy
97 system.cpu.icache.ReadReq_hits 791 # number of ReadReq hits
98 system.cpu.icache.demand_hits 791 # number of demand (read+write) hits
99 system.cpu.icache.overall_hits 791 # number of overall hits
100 system.cpu.icache.ReadReq_misses 347 # number of ReadReq misses
101 system.cpu.icache.demand_misses 347 # number of demand (read+write) misses
102 system.cpu.icache.overall_misses 347 # number of overall misses
103 system.cpu.icache.ReadReq_miss_latency 19110500 # number of ReadReq miss cycles
104 system.cpu.icache.demand_miss_latency 19110500 # number of demand (read+write) miss cycles
105 system.cpu.icache.overall_miss_latency 19110500 # number of overall miss cycles
106 system.cpu.icache.ReadReq_accesses 1138 # number of ReadReq accesses(hits+misses)
107 system.cpu.icache.demand_accesses 1138 # number of demand (read+write) accesses
108 system.cpu.icache.overall_accesses 1138 # number of overall (read+write) accesses
109 system.cpu.icache.ReadReq_miss_rate 0.304921 # miss rate for ReadReq accesses
110 system.cpu.icache.demand_miss_rate 0.304921 # miss rate for demand accesses
111 system.cpu.icache.overall_miss_rate 0.304921 # miss rate for overall accesses
112 system.cpu.icache.ReadReq_avg_miss_latency 55073.487032 # average ReadReq miss latency
113 system.cpu.icache.demand_avg_miss_latency 55073.487032 # average overall miss latency
114 system.cpu.icache.overall_avg_miss_latency 55073.487032 # average overall miss latency
115 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
116 system.cpu.icache.blocked_cycles::no_targets 104500 # number of cycles access was blocked
117 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
118 system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
119 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
120 system.cpu.icache.avg_blocked_cycles::no_targets 34833.333333 # average number of cycles each access was blocked
121 system.cpu.icache.fast_writes 0 # number of fast writes performed
122 system.cpu.icache.cache_copies 0 # number of cache copies performed
123 system.cpu.icache.writebacks 0 # number of writebacks
124 system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits
125 system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits
126 system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits
127 system.cpu.icache.ReadReq_mshr_misses 291 # number of ReadReq MSHR misses
128 system.cpu.icache.demand_mshr_misses 291 # number of demand (read+write) MSHR misses
129 system.cpu.icache.overall_mshr_misses 291 # number of overall MSHR misses
130 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
131 system.cpu.icache.ReadReq_mshr_miss_latency 15470000 # number of ReadReq MSHR miss cycles
132 system.cpu.icache.demand_mshr_miss_latency 15470000 # number of demand (read+write) MSHR miss cycles
133 system.cpu.icache.overall_mshr_miss_latency 15470000 # number of overall MSHR miss cycles
134 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
135 system.cpu.icache.ReadReq_mshr_miss_rate 0.255712 # mshr miss rate for ReadReq accesses
136 system.cpu.icache.demand_mshr_miss_rate 0.255712 # mshr miss rate for demand accesses
137 system.cpu.icache.overall_mshr_miss_rate 0.255712 # mshr miss rate for overall accesses
138 system.cpu.icache.ReadReq_avg_mshr_miss_latency 53161.512027 # average ReadReq mshr miss latency
139 system.cpu.icache.demand_avg_mshr_miss_latency 53161.512027 # average overall mshr miss latency
140 system.cpu.icache.overall_avg_mshr_miss_latency 53161.512027 # average overall mshr miss latency
141 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
142 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
143 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
144 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
145 system.cpu.dcache.replacements 0 # number of replacements
146 system.cpu.dcache.tagsinuse 82.859932 # Cycle average of tags in use
147 system.cpu.dcache.total_refs 1049 # Total number of references to valid blocks.
148 system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
149 system.cpu.dcache.avg_refs 7.770370 # Average number of references to valid blocks.
150 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
151 system.cpu.dcache.occ_blocks::0 82.859932 # Average occupied blocks per context
152 system.cpu.dcache.occ_percent::0 0.020229 # Average percentage of cache occupancy
153 system.cpu.dcache.ReadReq_hits 657 # number of ReadReq hits
154 system.cpu.dcache.WriteReq_hits 392 # number of WriteReq hits
155 system.cpu.dcache.demand_hits 1049 # number of demand (read+write) hits
156 system.cpu.dcache.overall_hits 1049 # number of overall hits
157 system.cpu.dcache.ReadReq_misses 59 # number of ReadReq misses
158 system.cpu.dcache.WriteReq_misses 281 # number of WriteReq misses
159 system.cpu.dcache.demand_misses 340 # number of demand (read+write) misses
160 system.cpu.dcache.overall_misses 340 # number of overall misses
161 system.cpu.dcache.ReadReq_miss_latency 3290500 # number of ReadReq miss cycles
162 system.cpu.dcache.WriteReq_miss_latency 15457500 # number of WriteReq miss cycles
163 system.cpu.dcache.demand_miss_latency 18748000 # number of demand (read+write) miss cycles
164 system.cpu.dcache.overall_miss_latency 18748000 # number of overall miss cycles
165 system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses)
166 system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses)
167 system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses
168 system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses
169 system.cpu.dcache.ReadReq_miss_rate 0.082402 # miss rate for ReadReq accesses
170 system.cpu.dcache.WriteReq_miss_rate 0.417533 # miss rate for WriteReq accesses
171 system.cpu.dcache.demand_miss_rate 0.244780 # miss rate for demand accesses
172 system.cpu.dcache.overall_miss_rate 0.244780 # miss rate for overall accesses
173 system.cpu.dcache.ReadReq_avg_miss_latency 55771.186441 # average ReadReq miss latency
174 system.cpu.dcache.WriteReq_avg_miss_latency 55008.896797 # average WriteReq miss latency
175 system.cpu.dcache.demand_avg_miss_latency 55141.176471 # average overall miss latency
176 system.cpu.dcache.overall_avg_miss_latency 55141.176471 # average overall miss latency
177 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
178 system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked
179 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
180 system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked
181 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
182 system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked
183 system.cpu.dcache.fast_writes 0 # number of fast writes performed
184 system.cpu.dcache.cache_copies 0 # number of cache copies performed
185 system.cpu.dcache.writebacks 0 # number of writebacks
186 system.cpu.dcache.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits
187 system.cpu.dcache.WriteReq_mshr_hits 200 # number of WriteReq MSHR hits
188 system.cpu.dcache.demand_mshr_hits 205 # number of demand (read+write) MSHR hits
189 system.cpu.dcache.overall_mshr_hits 205 # number of overall MSHR hits
190 system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
191 system.cpu.dcache.WriteReq_mshr_misses 81 # number of WriteReq MSHR misses
192 system.cpu.dcache.demand_mshr_misses 135 # number of demand (read+write) MSHR misses
193 system.cpu.dcache.overall_mshr_misses 135 # number of overall MSHR misses
194 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
195 system.cpu.dcache.ReadReq_mshr_miss_latency 2865500 # number of ReadReq MSHR miss cycles
196 system.cpu.dcache.WriteReq_mshr_miss_latency 4327000 # number of WriteReq MSHR miss cycles
197 system.cpu.dcache.demand_mshr_miss_latency 7192500 # number of demand (read+write) MSHR miss cycles
198 system.cpu.dcache.overall_mshr_miss_latency 7192500 # number of overall MSHR miss cycles
199 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
200 system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses
201 system.cpu.dcache.WriteReq_mshr_miss_rate 0.120357 # mshr miss rate for WriteReq accesses
202 system.cpu.dcache.demand_mshr_miss_rate 0.097192 # mshr miss rate for demand accesses
203 system.cpu.dcache.overall_mshr_miss_rate 0.097192 # mshr miss rate for overall accesses
204 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53064.814815 # average ReadReq mshr miss latency
205 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53419.753086 # average WriteReq mshr miss latency
206 system.cpu.dcache.demand_avg_mshr_miss_latency 53277.777778 # average overall mshr miss latency
207 system.cpu.dcache.overall_avg_mshr_miss_latency 53277.777778 # average overall mshr miss latency
208 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
209 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
210 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
211 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
212 system.cpu.l2cache.replacements 0 # number of replacements
213 system.cpu.l2cache.tagsinuse 162.297266 # Cycle average of tags in use
214 system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
215 system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks.
216 system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks.
217 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
218 system.cpu.l2cache.occ_blocks::0 162.297266 # Average occupied blocks per context
219 system.cpu.l2cache.occ_percent::0 0.004953 # Average percentage of cache occupancy
220 system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
221 system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
222 system.cpu.l2cache.overall_hits 3 # number of overall hits
223 system.cpu.l2cache.ReadReq_misses 342 # number of ReadReq misses
224 system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses
225 system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses
226 system.cpu.l2cache.overall_misses 423 # number of overall misses
227 system.cpu.l2cache.ReadReq_miss_latency 17918500 # number of ReadReq miss cycles
228 system.cpu.l2cache.ReadExReq_miss_latency 4230500 # number of ReadExReq miss cycles
229 system.cpu.l2cache.demand_miss_latency 22149000 # number of demand (read+write) miss cycles
230 system.cpu.l2cache.overall_miss_latency 22149000 # number of overall miss cycles
231 system.cpu.l2cache.ReadReq_accesses 345 # number of ReadReq accesses(hits+misses)
232 system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses)
233 system.cpu.l2cache.demand_accesses 426 # number of demand (read+write) accesses
234 system.cpu.l2cache.overall_accesses 426 # number of overall (read+write) accesses
235 system.cpu.l2cache.ReadReq_miss_rate 0.991304 # miss rate for ReadReq accesses
236 system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
237 system.cpu.l2cache.demand_miss_rate 0.992958 # miss rate for demand accesses
238 system.cpu.l2cache.overall_miss_rate 0.992958 # miss rate for overall accesses
239 system.cpu.l2cache.ReadReq_avg_miss_latency 52393.274854 # average ReadReq miss latency
240 system.cpu.l2cache.ReadExReq_avg_miss_latency 52228.395062 # average ReadExReq miss latency
241 system.cpu.l2cache.demand_avg_miss_latency 52361.702128 # average overall miss latency
242 system.cpu.l2cache.overall_avg_miss_latency 52361.702128 # average overall miss latency
243 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
244 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
245 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
246 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
247 system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
248 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
249 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
250 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
251 system.cpu.l2cache.writebacks 0 # number of writebacks
252 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
253 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
254 system.cpu.l2cache.ReadReq_mshr_misses 342 # number of ReadReq MSHR misses
255 system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses
256 system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses
257 system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses
258 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
259 system.cpu.l2cache.ReadReq_mshr_miss_latency 13747000 # number of ReadReq MSHR miss cycles
260 system.cpu.l2cache.ReadExReq_mshr_miss_latency 3255500 # number of ReadExReq MSHR miss cycles
261 system.cpu.l2cache.demand_mshr_miss_latency 17002500 # number of demand (read+write) MSHR miss cycles
262 system.cpu.l2cache.overall_mshr_miss_latency 17002500 # number of overall MSHR miss cycles
263 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
264 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.991304 # mshr miss rate for ReadReq accesses
265 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
266 system.cpu.l2cache.demand_mshr_miss_rate 0.992958 # mshr miss rate for demand accesses
267 system.cpu.l2cache.overall_mshr_miss_rate 0.992958 # mshr miss rate for overall accesses
268 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40195.906433 # average ReadReq mshr miss latency
269 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40191.358025 # average ReadExReq mshr miss latency
270 system.cpu.l2cache.demand_avg_mshr_miss_latency 40195.035461 # average overall mshr miss latency
271 system.cpu.l2cache.overall_avg_mshr_miss_latency 40195.035461 # average overall mshr miss latency
272 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
273 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
274 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
275 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
277 ---------- End Simulation Statistics ----------
projects / gem5.git / blob