2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 59245 # Simulator instruction rate (inst/s)
4 host_mem_usage 228168 # Number of bytes of host memory used
5 host_seconds 0.17 # Real time elapsed on the host
6 host_tick_rate 82238527 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 9809 # Number of instructions simulated
9 sim_seconds 0.000014 # Number of seconds simulated
10 sim_ticks 13637500 # Number of ticks simulated
11 system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
12 system.cpu.BPredUnit.BTBHits 715 # Number of BTB hits
13 system.cpu.BPredUnit.BTBLookups 1829 # Number of BTB lookups
14 system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
15 system.cpu.BPredUnit.condIncorrect 455 # Number of conditional branches incorrect
16 system.cpu.BPredUnit.condPredicted 1876 # Number of conditional branches predicted
17 system.cpu.BPredUnit.lookups 1876 # Number of BP lookups
18 system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
19 system.cpu.commit.COM:branches 1214 # Number of branches committed
20 system.cpu.commit.COM:bw_lim_events 22 # number cycles where commit BW limit reached
21 system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
22 system.cpu.commit.COM:committed_per_cycle::samples 15018 # Number of insts commited each cycle
23 system.cpu.commit.COM:committed_per_cycle::mean 0.653150 # Number of insts commited each cycle
24 system.cpu.commit.COM:committed_per_cycle::stdev 1.090994 # Number of insts commited each cycle
25 system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
26 system.cpu.commit.COM:committed_per_cycle::0 9552 63.60% 63.60% # Number of insts commited each cycle
27 system.cpu.commit.COM:committed_per_cycle::1 2996 19.95% 83.55% # Number of insts commited each cycle
28 system.cpu.commit.COM:committed_per_cycle::2 1196 7.96% 91.52% # Number of insts commited each cycle
29 system.cpu.commit.COM:committed_per_cycle::3 909 6.05% 97.57% # Number of insts commited each cycle
30 system.cpu.commit.COM:committed_per_cycle::4 244 1.62% 99.19% # Number of insts commited each cycle
31 system.cpu.commit.COM:committed_per_cycle::5 60 0.40% 99.59% # Number of insts commited each cycle
32 system.cpu.commit.COM:committed_per_cycle::6 31 0.21% 99.80% # Number of insts commited each cycle
33 system.cpu.commit.COM:committed_per_cycle::7 8 0.05% 99.85% # Number of insts commited each cycle
34 system.cpu.commit.COM:committed_per_cycle::8 22 0.15% 100.00% # Number of insts commited each cycle
35 system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
36 system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
37 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
38 system.cpu.commit.COM:committed_per_cycle::total 15018 # Number of insts commited each cycle
39 system.cpu.commit.COM:count 9809 # Number of instructions committed
40 system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
41 system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
42 system.cpu.commit.COM:int_insts 9714 # Number of committed integer instructions.
43 system.cpu.commit.COM:loads 1056 # Number of loads committed
44 system.cpu.commit.COM:membars 0 # Number of memory barriers committed
45 system.cpu.commit.COM:refs 1990 # Number of memory references committed
46 system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
47 system.cpu.commit.branchMispredicts 455 # The number of times a branch was mispredicted
48 system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions
49 system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
50 system.cpu.commit.commitSquashedInsts 3810 # The number of squashed insts skipped by commit
51 system.cpu.committedInsts 9809 # Number of Instructions Simulated
52 system.cpu.committedInsts_total 9809 # Number of Instructions Simulated
53 system.cpu.cpi 2.780712 # CPI: Cycles Per Instruction
54 system.cpu.cpi_total 2.780712 # CPI: Total CPI of All Threads
55 system.cpu.dcache.ReadReq_accesses 1299 # number of ReadReq accesses(hits+misses)
56 system.cpu.dcache.ReadReq_avg_miss_latency 34989.361702 # average ReadReq miss latency
57 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34992.307692 # average ReadReq mshr miss latency
58 system.cpu.dcache.ReadReq_hits 1205 # number of ReadReq hits
59 system.cpu.dcache.ReadReq_miss_latency 3289000 # number of ReadReq miss cycles
60 system.cpu.dcache.ReadReq_miss_rate 0.072363 # miss rate for ReadReq accesses
61 system.cpu.dcache.ReadReq_misses 94 # number of ReadReq misses
62 system.cpu.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits
63 system.cpu.dcache.ReadReq_mshr_miss_latency 2274500 # number of ReadReq MSHR miss cycles
64 system.cpu.dcache.ReadReq_mshr_miss_rate 0.050038 # mshr miss rate for ReadReq accesses
65 system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses
66 system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
67 system.cpu.dcache.WriteReq_avg_miss_latency 33138.977636 # average WriteReq miss latency
68 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35814.102564 # average WriteReq mshr miss latency
69 system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits
70 system.cpu.dcache.WriteReq_miss_latency 10372500 # number of WriteReq miss cycles
71 system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses
72 system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses
73 system.cpu.dcache.WriteReq_mshr_hits 235 # number of WriteReq MSHR hits
74 system.cpu.dcache.WriteReq_mshr_miss_latency 2793500 # number of WriteReq MSHR miss cycles
75 system.cpu.dcache.WriteReq_mshr_miss_rate 0.083512 # mshr miss rate for WriteReq accesses
76 system.cpu.dcache.WriteReq_mshr_misses 78 # number of WriteReq MSHR misses
77 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
78 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
79 system.cpu.dcache.avg_refs 12.859155 # Average number of references to valid blocks.
80 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
81 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
82 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
83 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
84 system.cpu.dcache.cache_copies 0 # number of cache copies performed
85 system.cpu.dcache.demand_accesses 2233 # number of demand (read+write) accesses
86 system.cpu.dcache.demand_avg_miss_latency 33566.339066 # average overall miss latency
87 system.cpu.dcache.demand_avg_mshr_miss_latency 35440.559441 # average overall mshr miss latency
88 system.cpu.dcache.demand_hits 1826 # number of demand (read+write) hits
89 system.cpu.dcache.demand_miss_latency 13661500 # number of demand (read+write) miss cycles
90 system.cpu.dcache.demand_miss_rate 0.182266 # miss rate for demand accesses
91 system.cpu.dcache.demand_misses 407 # number of demand (read+write) misses
92 system.cpu.dcache.demand_mshr_hits 264 # number of demand (read+write) MSHR hits
93 system.cpu.dcache.demand_mshr_miss_latency 5068000 # number of demand (read+write) MSHR miss cycles
94 system.cpu.dcache.demand_mshr_miss_rate 0.064039 # mshr miss rate for demand accesses
95 system.cpu.dcache.demand_mshr_misses 143 # number of demand (read+write) MSHR misses
96 system.cpu.dcache.fast_writes 0 # number of fast writes performed
97 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
98 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
99 system.cpu.dcache.occ_%::0 0.021266 # Average percentage of cache occupancy
100 system.cpu.dcache.occ_blocks::0 87.104239 # Average occupied blocks per context
101 system.cpu.dcache.overall_accesses 2233 # number of overall (read+write) accesses
102 system.cpu.dcache.overall_avg_miss_latency 33566.339066 # average overall miss latency
103 system.cpu.dcache.overall_avg_mshr_miss_latency 35440.559441 # average overall mshr miss latency
104 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
105 system.cpu.dcache.overall_hits 1826 # number of overall hits
106 system.cpu.dcache.overall_miss_latency 13661500 # number of overall miss cycles
107 system.cpu.dcache.overall_miss_rate 0.182266 # miss rate for overall accesses
108 system.cpu.dcache.overall_misses 407 # number of overall misses
109 system.cpu.dcache.overall_mshr_hits 264 # number of overall MSHR hits
110 system.cpu.dcache.overall_mshr_miss_latency 5068000 # number of overall MSHR miss cycles
111 system.cpu.dcache.overall_mshr_miss_rate 0.064039 # mshr miss rate for overall accesses
112 system.cpu.dcache.overall_mshr_misses 143 # number of overall MSHR misses
113 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
114 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
115 system.cpu.dcache.replacements 0 # number of replacements
116 system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks.
117 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
118 system.cpu.dcache.tagsinuse 87.104239 # Cycle average of tags in use
119 system.cpu.dcache.total_refs 1826 # Total number of references to valid blocks.
120 system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
121 system.cpu.dcache.writebacks 0 # number of writebacks
122 system.cpu.decode.DECODE:BlockedCycles 420 # Number of cycles decode is blocked
123 system.cpu.decode.DECODE:DecodedInsts 15296 # Number of instructions handled by decode
124 system.cpu.decode.DECODE:IdleCycles 6181 # Number of cycles decode is idle
125 system.cpu.decode.DECODE:RunCycles 8360 # Number of cycles decode is running
126 system.cpu.decode.DECODE:SquashCycles 701 # Number of cycles decode is squashing
127 system.cpu.decode.DECODE:UnblockCycles 57 # Number of cycles decode is unblocking
128 system.cpu.fetch.Branches 1876 # Number of branches that fetch encountered
129 system.cpu.fetch.CacheLines 1264 # Number of cache lines fetched
130 system.cpu.fetch.Cycles 9026 # Number of cycles fetch has run and was not squashing or blocked
131 system.cpu.fetch.IcacheSquashes 121 # Number of outstanding Icache misses that were squashed
132 system.cpu.fetch.Insts 8825 # Number of instructions fetch has processed
133 system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
134 system.cpu.fetch.SquashCycles 464 # Number of cycles fetch has spent squashing
135 system.cpu.fetch.branchRate 0.068778 # Number of branch fetches per cycle
136 system.cpu.fetch.icacheStallCycles 1264 # Number of cycles fetch is stalled on an Icache miss
137 system.cpu.fetch.predictedBranches 715 # Number of branches that fetch has predicted taken
138 system.cpu.fetch.rate 0.323545 # Number of inst fetches per cycle
139 system.cpu.fetch.rateDist::samples 15719 # Number of instructions fetched each cycle (Total)
140 system.cpu.fetch.rateDist::mean 1.009352 # Number of instructions fetched each cycle (Total)
141 system.cpu.fetch.rateDist::stdev 1.179835 # Number of instructions fetched each cycle (Total)
142 system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
143 system.cpu.fetch.rateDist::0 7007 44.58% 44.58% # Number of instructions fetched each cycle (Total)
144 system.cpu.fetch.rateDist::1 4504 28.65% 73.23% # Number of instructions fetched each cycle (Total)
145 system.cpu.fetch.rateDist::2 1838 11.69% 84.92% # Number of instructions fetched each cycle (Total)
146 system.cpu.fetch.rateDist::3 2072 13.18% 98.10% # Number of instructions fetched each cycle (Total)
147 system.cpu.fetch.rateDist::4 57 0.36% 98.47% # Number of instructions fetched each cycle (Total)
148 system.cpu.fetch.rateDist::5 222 1.41% 99.88% # Number of instructions fetched each cycle (Total)
149 system.cpu.fetch.rateDist::6 6 0.04% 99.92% # Number of instructions fetched each cycle (Total)
150 system.cpu.fetch.rateDist::7 8 0.05% 99.97% # Number of instructions fetched each cycle (Total)
151 system.cpu.fetch.rateDist::8 5 0.03% 100.00% # Number of instructions fetched each cycle (Total)
152 system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
153 system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
154 system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
155 system.cpu.fetch.rateDist::total 15719 # Number of instructions fetched each cycle (Total)
156 system.cpu.fp_regfile_reads 2 # number of floating regfile reads
157 system.cpu.icache.ReadReq_accesses 1264 # number of ReadReq accesses(hits+misses)
158 system.cpu.icache.ReadReq_avg_miss_latency 37405.594406 # average ReadReq miss latency
159 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35046.332046 # average ReadReq mshr miss latency
160 system.cpu.icache.ReadReq_hits 978 # number of ReadReq hits
161 system.cpu.icache.ReadReq_miss_latency 10698000 # number of ReadReq miss cycles
162 system.cpu.icache.ReadReq_miss_rate 0.226266 # miss rate for ReadReq accesses
163 system.cpu.icache.ReadReq_misses 286 # number of ReadReq misses
164 system.cpu.icache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits
165 system.cpu.icache.ReadReq_mshr_miss_latency 9077000 # number of ReadReq MSHR miss cycles
166 system.cpu.icache.ReadReq_mshr_miss_rate 0.204905 # mshr miss rate for ReadReq accesses
167 system.cpu.icache.ReadReq_mshr_misses 259 # number of ReadReq MSHR misses
168 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
169 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
170 system.cpu.icache.avg_refs 3.776062 # Average number of references to valid blocks.
171 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
172 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
173 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
174 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
175 system.cpu.icache.cache_copies 0 # number of cache copies performed
176 system.cpu.icache.demand_accesses 1264 # number of demand (read+write) accesses
177 system.cpu.icache.demand_avg_miss_latency 37405.594406 # average overall miss latency
178 system.cpu.icache.demand_avg_mshr_miss_latency 35046.332046 # average overall mshr miss latency
179 system.cpu.icache.demand_hits 978 # number of demand (read+write) hits
180 system.cpu.icache.demand_miss_latency 10698000 # number of demand (read+write) miss cycles
181 system.cpu.icache.demand_miss_rate 0.226266 # miss rate for demand accesses
182 system.cpu.icache.demand_misses 286 # number of demand (read+write) misses
183 system.cpu.icache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits
184 system.cpu.icache.demand_mshr_miss_latency 9077000 # number of demand (read+write) MSHR miss cycles
185 system.cpu.icache.demand_mshr_miss_rate 0.204905 # mshr miss rate for demand accesses
186 system.cpu.icache.demand_mshr_misses 259 # number of demand (read+write) MSHR misses
187 system.cpu.icache.fast_writes 0 # number of fast writes performed
188 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
189 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
190 system.cpu.icache.occ_%::0 0.062320 # Average percentage of cache occupancy
191 system.cpu.icache.occ_blocks::0 127.631724 # Average occupied blocks per context
192 system.cpu.icache.overall_accesses 1264 # number of overall (read+write) accesses
193 system.cpu.icache.overall_avg_miss_latency 37405.594406 # average overall miss latency
194 system.cpu.icache.overall_avg_mshr_miss_latency 35046.332046 # average overall mshr miss latency
195 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
196 system.cpu.icache.overall_hits 978 # number of overall hits
197 system.cpu.icache.overall_miss_latency 10698000 # number of overall miss cycles
198 system.cpu.icache.overall_miss_rate 0.226266 # miss rate for overall accesses
199 system.cpu.icache.overall_misses 286 # number of overall misses
200 system.cpu.icache.overall_mshr_hits 27 # number of overall MSHR hits
201 system.cpu.icache.overall_mshr_miss_latency 9077000 # number of overall MSHR miss cycles
202 system.cpu.icache.overall_mshr_miss_rate 0.204905 # mshr miss rate for overall accesses
203 system.cpu.icache.overall_mshr_misses 259 # number of overall MSHR misses
204 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
205 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
206 system.cpu.icache.replacements 0 # number of replacements
207 system.cpu.icache.sampled_refs 259 # Sample count of references to valid blocks.
208 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
209 system.cpu.icache.tagsinuse 127.631724 # Cycle average of tags in use
210 system.cpu.icache.total_refs 978 # Total number of references to valid blocks.
211 system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
212 system.cpu.icache.writebacks 0 # number of writebacks
213 system.cpu.idleCycles 11557 # Total number of cycles that the CPU has spent unscheduled due to idling
214 system.cpu.iew.EXEC:branches 1339 # Number of branches executed
215 system.cpu.iew.EXEC:nop 0 # number of nop insts executed
216 system.cpu.iew.EXEC:rate 0.445373 # Inst execution rate
217 system.cpu.iew.EXEC:refs 2437 # number of memory reference insts executed
218 system.cpu.iew.EXEC:stores 1088 # Number of stores executed
219 system.cpu.iew.EXEC:swp 0 # number of swp insts executed
220 system.cpu.iew.WB:consumers 9192 # num instructions consuming a value
221 system.cpu.iew.WB:count 11991 # cumulative count of insts written-back
222 system.cpu.iew.WB:fanout 0.803198 # average fanout of values written-back
223 system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
224 system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
225 system.cpu.iew.WB:producers 7383 # num instructions producing a value
226 system.cpu.iew.WB:rate 0.439617 # insts written-back per cycle
227 system.cpu.iew.WB:sent 12024 # cumulative count of insts sent to commit
228 system.cpu.iew.branchMispredicts 474 # Number of branch mispredicts detected at execute
229 system.cpu.iew.iewBlockCycles 40 # Number of cycles IEW is blocking
230 system.cpu.iew.iewDispLoadInsts 1510 # Number of dispatched load instructions
231 system.cpu.iew.iewDispNonSpecInsts 16 # Number of dispatched non-speculative instructions
232 system.cpu.iew.iewDispSquashedInsts 424 # Number of squashed instructions skipped by dispatch
233 system.cpu.iew.iewDispStoreInsts 1230 # Number of dispatched store instructions
234 system.cpu.iew.iewDispatchedInsts 13620 # Number of instructions dispatched to IQ
235 system.cpu.iew.iewExecLoadInsts 1349 # Number of load instructions executed
236 system.cpu.iew.iewExecSquashedInsts 556 # Number of squashed instructions skipped in execute
237 system.cpu.iew.iewExecutedInsts 12148 # Number of executed instructions
238 system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
239 system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
240 system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
241 system.cpu.iew.iewSquashCycles 701 # Number of cycles IEW is squashing
242 system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
243 system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
244 system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
245 system.cpu.iew.lsq.thread.0.forwLoads 23 # Number of loads that had data forwarded from stores
246 system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
247 system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
248 system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
249 system.cpu.iew.lsq.thread.0.memOrderViolation 10 # Number of memory ordering violations
250 system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
251 system.cpu.iew.lsq.thread.0.squashedLoads 454 # Number of loads squashed
252 system.cpu.iew.lsq.thread.0.squashedStores 296 # Number of stores squashed
253 system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
254 system.cpu.iew.predictedNotTakenIncorrect 385 # Number of branches that were predicted not taken incorrectly
255 system.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly
256 system.cpu.int_regfile_reads 19557 # number of integer regfile reads
257 system.cpu.int_regfile_writes 11326 # number of integer regfile writes
258 system.cpu.ipc 0.359620 # IPC: Instructions Per Cycle
259 system.cpu.ipc_total 0.359620 # IPC: Total IPC of All Threads
260 system.cpu.iq.ISSUE:FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
261 system.cpu.iq.ISSUE:FU_type_0::IntAlu 10141 79.83% 79.85% # Type of FU issued
262 system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 79.85% # Type of FU issued
263 system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 79.85% # Type of FU issued
264 system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 79.85% # Type of FU issued
265 system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 79.85% # Type of FU issued
266 system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 79.85% # Type of FU issued
267 system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 79.85% # Type of FU issued
268 system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 79.85% # Type of FU issued
269 system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 79.85% # Type of FU issued
270 system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 79.85% # Type of FU issued
271 system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 79.85% # Type of FU issued
272 system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 79.85% # Type of FU issued
273 system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 79.85% # Type of FU issued
274 system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 79.85% # Type of FU issued
275 system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 79.85% # Type of FU issued
276 system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 79.85% # Type of FU issued
277 system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 79.85% # Type of FU issued
278 system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 79.85% # Type of FU issued
279 system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 79.85% # Type of FU issued
280 system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 79.85% # Type of FU issued
281 system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 79.85% # Type of FU issued
282 system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 79.85% # Type of FU issued
283 system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 79.85% # Type of FU issued
284 system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 79.85% # Type of FU issued
285 system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 79.85% # Type of FU issued
286 system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 79.85% # Type of FU issued
287 system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 79.85% # Type of FU issued
288 system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 79.85% # Type of FU issued
289 system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 79.85% # Type of FU issued
290 system.cpu.iq.ISSUE:FU_type_0::MemRead 1414 11.13% 90.98% # Type of FU issued
291 system.cpu.iq.ISSUE:FU_type_0::MemWrite 1146 9.02% 100.00% # Type of FU issued
292 system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
293 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
294 system.cpu.iq.ISSUE:FU_type_0::total 12704 # Type of FU issued
295 system.cpu.iq.ISSUE:fu_busy_cnt 4 # FU busy when requested
296 system.cpu.iq.ISSUE:fu_busy_rate 0.000315 # FU busy rate (busy events/executed inst)
297 system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
298 system.cpu.iq.ISSUE:fu_full::IntAlu 0 0.00% 0.00% # attempts to use FU when none available
299 system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available
300 system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available
301 system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available
302 system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available
303 system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available
304 system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available
305 system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available
306 system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
307 system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available
308 system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available
309 system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available
310 system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available
311 system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available
312 system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available
313 system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available
314 system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available
315 system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available
316 system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available
317 system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available
318 system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available
319 system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available
320 system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available
321 system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available
322 system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available
323 system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available
324 system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available
325 system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available
326 system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
327 system.cpu.iq.ISSUE:fu_full::MemRead 4 100.00% 100.00% # attempts to use FU when none available
328 system.cpu.iq.ISSUE:fu_full::MemWrite 0 0.00% 100.00% # attempts to use FU when none available
329 system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
330 system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
331 system.cpu.iq.ISSUE:issued_per_cycle::samples 15719 # Number of insts issued each cycle
332 system.cpu.iq.ISSUE:issued_per_cycle::mean 0.808194 # Number of insts issued each cycle
333 system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.980491 # Number of insts issued each cycle
334 system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
335 system.cpu.iq.ISSUE:issued_per_cycle::0 7896 50.23% 50.23% # Number of insts issued each cycle
336 system.cpu.iq.ISSUE:issued_per_cycle::1 4146 26.38% 76.61% # Number of insts issued each cycle
337 system.cpu.iq.ISSUE:issued_per_cycle::2 2688 17.10% 93.71% # Number of insts issued each cycle
338 system.cpu.iq.ISSUE:issued_per_cycle::3 806 5.13% 98.84% # Number of insts issued each cycle
339 system.cpu.iq.ISSUE:issued_per_cycle::4 156 0.99% 99.83% # Number of insts issued each cycle
340 system.cpu.iq.ISSUE:issued_per_cycle::5 22 0.14% 99.97% # Number of insts issued each cycle
341 system.cpu.iq.ISSUE:issued_per_cycle::6 5 0.03% 100.00% # Number of insts issued each cycle
342 system.cpu.iq.ISSUE:issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
343 system.cpu.iq.ISSUE:issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
344 system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
345 system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
346 system.cpu.iq.ISSUE:issued_per_cycle::max_value 6 # Number of insts issued each cycle
347 system.cpu.iq.ISSUE:issued_per_cycle::total 15719 # Number of insts issued each cycle
348 system.cpu.iq.ISSUE:rate 0.465757 # Inst issue rate
349 system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
350 system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
351 system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
352 system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes
353 system.cpu.iq.int_alu_accesses 12701 # Number of integer alu accesses
354 system.cpu.iq.int_inst_queue_reads 41124 # Number of integer instruction queue reads
355 system.cpu.iq.int_inst_queue_wakeup_accesses 11989 # Number of integer instruction queue wakeup accesses
356 system.cpu.iq.int_inst_queue_writes 16903 # Number of integer instruction queue writes
357 system.cpu.iq.iqInstsAdded 13604 # Number of instructions added to the IQ (excludes non-spec)
358 system.cpu.iq.iqInstsIssued 12704 # Number of instructions issued
359 system.cpu.iq.iqNonSpecInstsAdded 16 # Number of non-speculative instructions added to the IQ
360 system.cpu.iq.iqSquashedInstsExamined 3282 # Number of squashed instructions iterated over during squash; mainly for profiling
361 system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
362 system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
363 system.cpu.iq.iqSquashedOperandsExamined 3903 # Number of squashed operands that are examined and possibly removed from graph
364 system.cpu.l2cache.ReadExReq_accesses 78 # number of ReadExReq accesses(hits+misses)
365 system.cpu.l2cache.ReadExReq_avg_miss_latency 34512.820513 # average ReadExReq miss latency
366 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31358.974359 # average ReadExReq mshr miss latency
367 system.cpu.l2cache.ReadExReq_miss_latency 2692000 # number of ReadExReq miss cycles
368 system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
369 system.cpu.l2cache.ReadExReq_misses 78 # number of ReadExReq misses
370 system.cpu.l2cache.ReadExReq_mshr_miss_latency 2446000 # number of ReadExReq MSHR miss cycles
371 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
372 system.cpu.l2cache.ReadExReq_mshr_misses 78 # number of ReadExReq MSHR misses
373 system.cpu.l2cache.ReadReq_accesses 324 # number of ReadReq accesses(hits+misses)
374 system.cpu.l2cache.ReadReq_avg_miss_latency 34181.677019 # average ReadReq miss latency
375 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 30998.447205 # average ReadReq mshr miss latency
376 system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
377 system.cpu.l2cache.ReadReq_miss_latency 11006500 # number of ReadReq miss cycles
378 system.cpu.l2cache.ReadReq_miss_rate 0.993827 # miss rate for ReadReq accesses
379 system.cpu.l2cache.ReadReq_misses 322 # number of ReadReq misses
380 system.cpu.l2cache.ReadReq_mshr_miss_latency 9981500 # number of ReadReq MSHR miss cycles
381 system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993827 # mshr miss rate for ReadReq accesses
382 system.cpu.l2cache.ReadReq_mshr_misses 322 # number of ReadReq MSHR misses
383 system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
384 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
385 system.cpu.l2cache.avg_refs 0.006231 # Average number of references to valid blocks.
386 system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
387 system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
388 system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
389 system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
390 system.cpu.l2cache.cache_copies 0 # number of cache copies performed
391 system.cpu.l2cache.demand_accesses 402 # number of demand (read+write) accesses
392 system.cpu.l2cache.demand_avg_miss_latency 34246.250000 # average overall miss latency
393 system.cpu.l2cache.demand_avg_mshr_miss_latency 31068.750000 # average overall mshr miss latency
394 system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
395 system.cpu.l2cache.demand_miss_latency 13698500 # number of demand (read+write) miss cycles
396 system.cpu.l2cache.demand_miss_rate 0.995025 # miss rate for demand accesses
397 system.cpu.l2cache.demand_misses 400 # number of demand (read+write) misses
398 system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
399 system.cpu.l2cache.demand_mshr_miss_latency 12427500 # number of demand (read+write) MSHR miss cycles
400 system.cpu.l2cache.demand_mshr_miss_rate 0.995025 # mshr miss rate for demand accesses
401 system.cpu.l2cache.demand_mshr_misses 400 # number of demand (read+write) MSHR misses
402 system.cpu.l2cache.fast_writes 0 # number of fast writes performed
403 system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
404 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
405 system.cpu.l2cache.occ_%::0 0.004917 # Average percentage of cache occupancy
406 system.cpu.l2cache.occ_blocks::0 161.123348 # Average occupied blocks per context
407 system.cpu.l2cache.overall_accesses 402 # number of overall (read+write) accesses
408 system.cpu.l2cache.overall_avg_miss_latency 34246.250000 # average overall miss latency
409 system.cpu.l2cache.overall_avg_mshr_miss_latency 31068.750000 # average overall mshr miss latency
410 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
411 system.cpu.l2cache.overall_hits 2 # number of overall hits
412 system.cpu.l2cache.overall_miss_latency 13698500 # number of overall miss cycles
413 system.cpu.l2cache.overall_miss_rate 0.995025 # miss rate for overall accesses
414 system.cpu.l2cache.overall_misses 400 # number of overall misses
415 system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
416 system.cpu.l2cache.overall_mshr_miss_latency 12427500 # number of overall MSHR miss cycles
417 system.cpu.l2cache.overall_mshr_miss_rate 0.995025 # mshr miss rate for overall accesses
418 system.cpu.l2cache.overall_mshr_misses 400 # number of overall MSHR misses
419 system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
420 system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
421 system.cpu.l2cache.replacements 0 # number of replacements
422 system.cpu.l2cache.sampled_refs 321 # Sample count of references to valid blocks.
423 system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
424 system.cpu.l2cache.tagsinuse 161.123348 # Cycle average of tags in use
425 system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
426 system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
427 system.cpu.l2cache.writebacks 0 # number of writebacks
428 system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
429 system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
430 system.cpu.memDep0.insertedLoads 1510 # Number of loads inserted to the mem dependence unit.
431 system.cpu.memDep0.insertedStores 1230 # Number of stores inserted to the mem dependence unit.
432 system.cpu.misc_regfile_reads 5444 # number of misc regfile reads
433 system.cpu.numCycles 27276 # number of cpu cycles simulated
434 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
435 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
436 system.cpu.rename.RENAME:BlockCycles 87 # Number of cycles rename is blocking
437 system.cpu.rename.RENAME:CommittedMaps 9368 # Number of HB maps that are committed
438 system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full
439 system.cpu.rename.RENAME:IdleCycles 6548 # Number of cycles rename is idle
440 system.cpu.rename.RENAME:LSQFullEvents 15 # Number of times rename has blocked due to LSQ full
441 system.cpu.rename.RENAME:RenameLookups 31415 # Number of register rename lookups that rename has made
442 system.cpu.rename.RENAME:RenamedInsts 14729 # Number of instructions processed by rename
443 system.cpu.rename.RENAME:RenamedOperands 13866 # Number of destination operands rename has renamed
444 system.cpu.rename.RENAME:RunCycles 8021 # Number of cycles rename is running
445 system.cpu.rename.RENAME:SquashCycles 701 # Number of cycles rename is squashing
446 system.cpu.rename.RENAME:UnblockCycles 105 # Number of cycles rename is unblocking
447 system.cpu.rename.RENAME:UndoneMaps 4498 # Number of HB maps that are undone due to squashing
448 system.cpu.rename.RENAME:fp_rename_lookups 16 # Number of floating rename lookups
449 system.cpu.rename.RENAME:int_rename_lookups 31399 # Number of integer rename lookups
450 system.cpu.rename.RENAME:serializeStallCycles 257 # count of cycles rename stalled for serializing inst
451 system.cpu.rename.RENAME:serializingInsts 19 # count of serializing insts renamed
452 system.cpu.rename.RENAME:skidInsts 159 # count of insts added to the skid buffer
453 system.cpu.rename.RENAME:tempSerializingInsts 16 # count of temporary serializing insts renamed
454 system.cpu.rob.rob_reads 28615 # The number of ROB reads
455 system.cpu.rob.rob_writes 27943 # The number of ROB writes
456 system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself
457 system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
459 ---------- End Simulation Statistics ----------
projects / gem5.git / blob