tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout

   1 M5 Simulator System
   2
   3 Copyright (c) 2001-2008
   4 The Regents of The University of Michigan
   5 All Rights Reserved
   6
   7
   8 M5 compiled Feb 25 2010 03:11:27
   9 M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
  10 M5 started Feb 25 2010 03:38:00
  11 M5 executing on SC2B0619
  12 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing
  13 Global frequency set at 1000000000000 ticks per second
  14 info: Entering event queue @ 0.  Starting simulation...
  15 Begining test of difficult SPARC instructions...
  16 LDSTUB:         Passed
  17 SWAP:           Passed
  18 CAS FAIL:       Passed
  19 CAS WORK:       Passed
  20 CASX FAIL:      Passed
  21 CASX WORK:      Passed
  22 LDTX:           Passed
  23 LDTW:           Passed
  24 STTW:           Passed
  25 Done
  26 Exiting @ tick 27756500 because target called exit()