2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 1870819 # Simulator instruction rate (inst/s)
4 host_mem_usage 272832 # Number of bytes of host memory used
5 host_seconds 30.04 # Real time elapsed on the host
6 host_tick_rate 64245310717 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 56205703 # Number of instructions simulated
9 sim_seconds 1.930165 # Number of seconds simulated
10 sim_ticks 1930164593000 # Number of ticks simulated
11 system.cpu.dcache.LoadLockedReq_accesses 200404 # number of LoadLockedReq accesses(hits+misses)
12 system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.546017 # average LoadLockedReq miss latency
13 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.546017 # average LoadLockedReq mshr miss latency
14 system.cpu.dcache.LoadLockedReq_hits 183095 # number of LoadLockedReq hits
15 system.cpu.dcache.LoadLockedReq_miss_latency 248584000 # number of LoadLockedReq miss cycles
16 system.cpu.dcache.LoadLockedReq_miss_rate 0.086371 # miss rate for LoadLockedReq accesses
17 system.cpu.dcache.LoadLockedReq_misses 17309 # number of LoadLockedReq misses
18 system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196657000 # number of LoadLockedReq MSHR miss cycles
19 system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086371 # mshr miss rate for LoadLockedReq accesses
20 system.cpu.dcache.LoadLockedReq_mshr_misses 17309 # number of LoadLockedReq MSHR misses
21 system.cpu.dcache.ReadReq_accesses 8888653 # number of ReadReq accesses(hits+misses)
22 system.cpu.dcache.ReadReq_avg_miss_latency 25452.354477 # average ReadReq miss latency
23 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.311493 # average ReadReq mshr miss latency
24 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
25 system.cpu.dcache.ReadReq_hits 7818479 # number of ReadReq hits
26 system.cpu.dcache.ReadReq_miss_latency 27238448000 # number of ReadReq miss cycles
27 system.cpu.dcache.ReadReq_miss_rate 0.120398 # miss rate for ReadReq accesses
28 system.cpu.dcache.ReadReq_misses 1070174 # number of ReadReq misses
29 system.cpu.dcache.ReadReq_mshr_miss_latency 24027880000 # number of ReadReq MSHR miss cycles
30 system.cpu.dcache.ReadReq_mshr_miss_rate 0.120398 # mshr miss rate for ReadReq accesses
31 system.cpu.dcache.ReadReq_mshr_misses 1070174 # number of ReadReq MSHR misses
32 system.cpu.dcache.ReadReq_mshr_uncacheable_latency 862763000 # number of ReadReq MSHR uncacheable cycles
33 system.cpu.dcache.StoreCondReq_accesses 199383 # number of StoreCondReq accesses(hits+misses)
34 system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.366085 # average StoreCondReq miss latency
35 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.366085 # average StoreCondReq mshr miss latency
36 system.cpu.dcache.StoreCondReq_hits 169379 # number of StoreCondReq hits
37 system.cpu.dcache.StoreCondReq_miss_latency 1680355000 # number of StoreCondReq miss cycles
38 system.cpu.dcache.StoreCondReq_miss_rate 0.150484 # miss rate for StoreCondReq accesses
39 system.cpu.dcache.StoreCondReq_misses 30004 # number of StoreCondReq misses
40 system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590343000 # number of StoreCondReq MSHR miss cycles
41 system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150484 # mshr miss rate for StoreCondReq accesses
42 system.cpu.dcache.StoreCondReq_mshr_misses 30004 # number of StoreCondReq MSHR misses
43 system.cpu.dcache.WriteReq_accesses 6160337 # number of WriteReq accesses(hits+misses)
44 system.cpu.dcache.WriteReq_avg_miss_latency 56004.022652 # average WriteReq miss latency
45 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.022652 # average WriteReq mshr miss latency
46 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
47 system.cpu.dcache.WriteReq_hits 5759482 # number of WriteReq hits
48 system.cpu.dcache.WriteReq_miss_latency 22449492500 # number of WriteReq miss cycles
49 system.cpu.dcache.WriteReq_miss_rate 0.065070 # miss rate for WriteReq accesses
50 system.cpu.dcache.WriteReq_misses 400855 # number of WriteReq misses
51 system.cpu.dcache.WriteReq_mshr_miss_latency 21246927500 # number of WriteReq MSHR miss cycles
52 system.cpu.dcache.WriteReq_mshr_miss_rate 0.065070 # mshr miss rate for WriteReq accesses
53 system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses
54 system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1201243500 # number of WriteReq MSHR uncacheable cycles
55 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
56 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
57 system.cpu.dcache.avg_refs 10.097318 # Average number of references to valid blocks.
58 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
59 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
60 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
61 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
62 system.cpu.dcache.cache_copies 0 # number of cache copies performed
63 system.cpu.dcache.demand_accesses 15048990 # number of demand (read+write) accesses
64 system.cpu.dcache.demand_avg_miss_latency 33777.675695 # average overall miss latency
65 system.cpu.dcache.demand_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency
66 system.cpu.dcache.demand_hits 13577961 # number of demand (read+write) hits
67 system.cpu.dcache.demand_miss_latency 49687940500 # number of demand (read+write) miss cycles
68 system.cpu.dcache.demand_miss_rate 0.097749 # miss rate for demand accesses
69 system.cpu.dcache.demand_misses 1471029 # number of demand (read+write) misses
70 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
71 system.cpu.dcache.demand_mshr_miss_latency 45274807500 # number of demand (read+write) MSHR miss cycles
72 system.cpu.dcache.demand_mshr_miss_rate 0.097749 # mshr miss rate for demand accesses
73 system.cpu.dcache.demand_mshr_misses 1471029 # number of demand (read+write) MSHR misses
74 system.cpu.dcache.fast_writes 0 # number of fast writes performed
75 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
76 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
77 system.cpu.dcache.overall_accesses 15048990 # number of overall (read+write) accesses
78 system.cpu.dcache.overall_avg_miss_latency 33777.675695 # average overall miss latency
79 system.cpu.dcache.overall_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency
80 system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
81 system.cpu.dcache.overall_hits 13577961 # number of overall hits
82 system.cpu.dcache.overall_miss_latency 49687940500 # number of overall miss cycles
83 system.cpu.dcache.overall_miss_rate 0.097749 # miss rate for overall accesses
84 system.cpu.dcache.overall_misses 1471029 # number of overall misses
85 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
86 system.cpu.dcache.overall_mshr_miss_latency 45274807500 # number of overall MSHR miss cycles
87 system.cpu.dcache.overall_mshr_miss_rate 0.097749 # mshr miss rate for overall accesses
88 system.cpu.dcache.overall_mshr_misses 1471029 # number of overall MSHR misses
89 system.cpu.dcache.overall_mshr_uncacheable_latency 2064006500 # number of overall MSHR uncacheable cycles
90 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
91 system.cpu.dcache.replacements 1391606 # number of replacements
92 system.cpu.dcache.sampled_refs 1392118 # Sample count of references to valid blocks.
93 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
94 system.cpu.dcache.tagsinuse 511.984142 # Cycle average of tags in use
95 system.cpu.dcache.total_refs 14056658 # Total number of references to valid blocks.
96 system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit.
97 system.cpu.dcache.writebacks 430459 # number of writebacks
98 system.cpu.dtb.data_accesses 1020784 # DTB accesses
99 system.cpu.dtb.data_acv 367 # DTB access violations
100 system.cpu.dtb.data_hits 15429793 # DTB hits
101 system.cpu.dtb.data_misses 11466 # DTB misses
102 system.cpu.dtb.fetch_accesses 0 # ITB accesses
103 system.cpu.dtb.fetch_acv 0 # ITB acv
104 system.cpu.dtb.fetch_hits 0 # ITB hits
105 system.cpu.dtb.fetch_misses 0 # ITB misses
106 system.cpu.dtb.read_accesses 728853 # DTB read accesses
107 system.cpu.dtb.read_acv 210 # DTB read access violations
108 system.cpu.dtb.read_hits 9069700 # DTB read hits
109 system.cpu.dtb.read_misses 10324 # DTB read misses
110 system.cpu.dtb.write_accesses 291931 # DTB write accesses
111 system.cpu.dtb.write_acv 157 # DTB write access violations
112 system.cpu.dtb.write_hits 6360093 # DTB write hits
113 system.cpu.dtb.write_misses 1142 # DTB write misses
114 system.cpu.icache.ReadReq_accesses 56217537 # number of ReadReq accesses(hits+misses)
115 system.cpu.icache.ReadReq_avg_miss_latency 14711.221983 # average ReadReq miss latency
116 system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.491665 # average ReadReq mshr miss latency
117 system.cpu.icache.ReadReq_hits 55286436 # number of ReadReq hits
118 system.cpu.icache.ReadReq_miss_latency 13697633500 # number of ReadReq miss cycles
119 system.cpu.icache.ReadReq_miss_rate 0.016562 # miss rate for ReadReq accesses
120 system.cpu.icache.ReadReq_misses 931101 # number of ReadReq misses
121 system.cpu.icache.ReadReq_mshr_miss_latency 10903650500 # number of ReadReq MSHR miss cycles
122 system.cpu.icache.ReadReq_mshr_miss_rate 0.016562 # mshr miss rate for ReadReq accesses
123 system.cpu.icache.ReadReq_mshr_misses 931101 # number of ReadReq MSHR misses
124 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
125 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
126 system.cpu.icache.avg_refs 59.387754 # Average number of references to valid blocks.
127 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
128 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
129 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
130 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
131 system.cpu.icache.cache_copies 0 # number of cache copies performed
132 system.cpu.icache.demand_accesses 56217537 # number of demand (read+write) accesses
133 system.cpu.icache.demand_avg_miss_latency 14711.221983 # average overall miss latency
134 system.cpu.icache.demand_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency
135 system.cpu.icache.demand_hits 55286436 # number of demand (read+write) hits
136 system.cpu.icache.demand_miss_latency 13697633500 # number of demand (read+write) miss cycles
137 system.cpu.icache.demand_miss_rate 0.016562 # miss rate for demand accesses
138 system.cpu.icache.demand_misses 931101 # number of demand (read+write) misses
139 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
140 system.cpu.icache.demand_mshr_miss_latency 10903650500 # number of demand (read+write) MSHR miss cycles
141 system.cpu.icache.demand_mshr_miss_rate 0.016562 # mshr miss rate for demand accesses
142 system.cpu.icache.demand_mshr_misses 931101 # number of demand (read+write) MSHR misses
143 system.cpu.icache.fast_writes 0 # number of fast writes performed
144 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
145 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
146 system.cpu.icache.overall_accesses 56217537 # number of overall (read+write) accesses
147 system.cpu.icache.overall_avg_miss_latency 14711.221983 # average overall miss latency
148 system.cpu.icache.overall_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency
149 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
150 system.cpu.icache.overall_hits 55286436 # number of overall hits
151 system.cpu.icache.overall_miss_latency 13697633500 # number of overall miss cycles
152 system.cpu.icache.overall_miss_rate 0.016562 # miss rate for overall accesses
153 system.cpu.icache.overall_misses 931101 # number of overall misses
154 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
155 system.cpu.icache.overall_mshr_miss_latency 10903650500 # number of overall MSHR miss cycles
156 system.cpu.icache.overall_mshr_miss_rate 0.016562 # mshr miss rate for overall accesses
157 system.cpu.icache.overall_mshr_misses 931101 # number of overall MSHR misses
158 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
159 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
160 system.cpu.icache.replacements 930429 # number of replacements
161 system.cpu.icache.sampled_refs 930940 # Sample count of references to valid blocks.
162 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
163 system.cpu.icache.tagsinuse 508.559728 # Cycle average of tags in use
164 system.cpu.icache.total_refs 55286436 # Total number of references to valid blocks.
165 system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit.
166 system.cpu.icache.writebacks 0 # number of writebacks
167 system.cpu.idle_fraction 0.929209 # Percentage of idle cycles
168 system.cpu.itb.data_accesses 0 # DTB accesses
169 system.cpu.itb.data_acv 0 # DTB access violations
170 system.cpu.itb.data_hits 0 # DTB hits
171 system.cpu.itb.data_misses 0 # DTB misses
172 system.cpu.itb.fetch_accesses 4982987 # ITB accesses
173 system.cpu.itb.fetch_acv 184 # ITB acv
174 system.cpu.itb.fetch_hits 4977977 # ITB hits
175 system.cpu.itb.fetch_misses 5010 # ITB misses
176 system.cpu.itb.read_accesses 0 # DTB read accesses
177 system.cpu.itb.read_acv 0 # DTB read access violations
178 system.cpu.itb.read_hits 0 # DTB read hits
179 system.cpu.itb.read_misses 0 # DTB read misses
180 system.cpu.itb.write_accesses 0 # DTB write accesses
181 system.cpu.itb.write_acv 0 # DTB write access violations
182 system.cpu.itb.write_hits 0 # DTB write hits
183 system.cpu.itb.write_misses 0 # DTB write misses
184 system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
185 system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
186 system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
187 system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
188 system.cpu.kern.callpal::swpctx 4171 2.16% 2.16% # number of callpals executed
189 system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
190 system.cpu.kern.callpal::wrent 7 0.00% 2.19% # number of callpals executed
191 system.cpu.kern.callpal::swpipl 176257 91.22% 93.41% # number of callpals executed
192 system.cpu.kern.callpal::rdps 6844 3.54% 96.95% # number of callpals executed
193 system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
194 system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
195 system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
196 system.cpu.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed
197 system.cpu.kern.callpal::rti 5169 2.68% 99.64% # number of callpals executed
198 system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
199 system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
200 system.cpu.kern.callpal::total 193221 # number of callpals executed
201 system.cpu.kern.inst.arm 0 # number of arm instructions executed
202 system.cpu.kern.inst.hwrei 212325 # number of hwrei instructions executed
203 system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed
204 system.cpu.kern.ipl_count::0 75001 40.87% 40.87% # number of times we switched to this ipl
205 system.cpu.kern.ipl_count::21 131 0.07% 40.94% # number of times we switched to this ipl
206 system.cpu.kern.ipl_count::22 1944 1.06% 42.00% # number of times we switched to this ipl
207 system.cpu.kern.ipl_count::31 106426 58.00% 100.00% # number of times we switched to this ipl
208 system.cpu.kern.ipl_count::total 183502 # number of times we switched to this ipl
209 system.cpu.kern.ipl_good::0 73634 49.31% 49.31% # number of times we switched to this ipl from a different ipl
210 system.cpu.kern.ipl_good::21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl
211 system.cpu.kern.ipl_good::22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl
212 system.cpu.kern.ipl_good::31 73634 49.31% 100.00% # number of times we switched to this ipl from a different ipl
213 system.cpu.kern.ipl_good::total 149343 # number of times we switched to this ipl from a different ipl
214 system.cpu.kern.ipl_ticks::0 1866810523000 96.72% 96.72% # number of cycles we spent at this ipl
215 system.cpu.kern.ipl_ticks::21 96331500 0.00% 96.72% # number of cycles we spent at this ipl
216 system.cpu.kern.ipl_ticks::22 565310500 0.03% 96.75% # number of cycles we spent at this ipl
217 system.cpu.kern.ipl_ticks::31 62691670000 3.25% 100.00% # number of cycles we spent at this ipl
218 system.cpu.kern.ipl_ticks::total 1930163835000 # number of cycles we spent at this ipl
219 system.cpu.kern.ipl_used::0 0.981774 # fraction of swpipl calls that actually changed the ipl
220 system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
221 system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
222 system.cpu.kern.ipl_used::31 0.691880 # fraction of swpipl calls that actually changed the ipl
223 system.cpu.kern.mode_good::kernel 1911
224 system.cpu.kern.mode_good::user 1744
225 system.cpu.kern.mode_good::idle 167
226 system.cpu.kern.mode_switch::kernel 5917 # number of protection mode switches
227 system.cpu.kern.mode_switch::user 1744 # number of protection mode switches
228 system.cpu.kern.mode_switch::idle 2089 # number of protection mode switches
229 system.cpu.kern.mode_switch_good::kernel 0.322968 # fraction of useful protection mode switches
230 system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
231 system.cpu.kern.mode_switch_good::idle 0.079943 # fraction of useful protection mode switches
232 system.cpu.kern.mode_switch_good::total 1.402910 # fraction of useful protection mode switches
233 system.cpu.kern.mode_ticks::kernel 48447088000 2.51% 2.51% # number of ticks spent at the given mode
234 system.cpu.kern.mode_ticks::user 5539986000 0.29% 2.80% # number of ticks spent at the given mode
235 system.cpu.kern.mode_ticks::idle 1876176759000 97.20% 100.00% # number of ticks spent at the given mode
236 system.cpu.kern.swap_context 4172 # number of times the context was actually changed
237 system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
238 system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
239 system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
240 system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
241 system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
242 system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
243 system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
244 system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
245 system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
246 system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
247 system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
248 system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
249 system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
250 system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
251 system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
252 system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
253 system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
254 system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
255 system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
256 system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
257 system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
258 system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
259 system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
260 system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
261 system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
262 system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
263 system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
264 system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
265 system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
266 system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
267 system.cpu.kern.syscall::total 326 # number of syscalls executed
268 system.cpu.not_idle_fraction 0.070791 # Percentage of non-idle cycles
269 system.cpu.numCycles 3860329186 # number of cpu cycles simulated
270 system.cpu.num_insts 56205703 # Number of instructions executed
271 system.cpu.num_refs 15677891 # Number of memory references
272 system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
273 system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
274 system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
275 system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
276 system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
277 system.disk0.dma_write_txs 395 # Number of DMA write transactions.
278 system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
279 system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
280 system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
281 system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
282 system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
283 system.disk2.dma_write_txs 1 # Number of DMA write transactions.
284 system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses)
285 system.iocache.ReadReq_avg_miss_latency 115254.323699 # average ReadReq miss latency
286 system.iocache.ReadReq_avg_mshr_miss_latency 63254.323699 # average ReadReq mshr miss latency
287 system.iocache.ReadReq_miss_latency 19938998 # number of ReadReq miss cycles
288 system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
289 system.iocache.ReadReq_misses 173 # number of ReadReq misses
290 system.iocache.ReadReq_mshr_miss_latency 10942998 # number of ReadReq MSHR miss cycles
291 system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
292 system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
293 system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
294 system.iocache.WriteReq_avg_miss_latency 137876.559636 # average WriteReq miss latency
295 system.iocache.WriteReq_avg_mshr_miss_latency 85873.072921 # average WriteReq mshr miss latency
296 system.iocache.WriteReq_miss_latency 5729046806 # number of WriteReq miss cycles
297 system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
298 system.iocache.WriteReq_misses 41552 # number of WriteReq misses
299 system.iocache.WriteReq_mshr_miss_latency 3568197926 # number of WriteReq MSHR miss cycles
300 system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
301 system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
302 system.iocache.avg_blocked_cycles::no_mshrs 6163.674943 # average number of cycles each access was blocked
303 system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
304 system.iocache.avg_refs 0 # Average number of references to valid blocks.
305 system.iocache.blocked::no_mshrs 10472 # number of cycles access was blocked
306 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
307 system.iocache.blocked_cycles::no_mshrs 64546004 # number of cycles access was blocked
308 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
309 system.iocache.cache_copies 0 # number of cache copies performed
310 system.iocache.demand_accesses 41725 # number of demand (read+write) accesses
311 system.iocache.demand_avg_miss_latency 137782.763427 # average overall miss latency
312 system.iocache.demand_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency
313 system.iocache.demand_hits 0 # number of demand (read+write) hits
314 system.iocache.demand_miss_latency 5748985804 # number of demand (read+write) miss cycles
315 system.iocache.demand_miss_rate 1 # miss rate for demand accesses
316 system.iocache.demand_misses 41725 # number of demand (read+write) misses
317 system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
318 system.iocache.demand_mshr_miss_latency 3579140924 # number of demand (read+write) MSHR miss cycles
319 system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
320 system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
321 system.iocache.fast_writes 0 # number of fast writes performed
322 system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
323 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
324 system.iocache.overall_accesses 41725 # number of overall (read+write) accesses
325 system.iocache.overall_avg_miss_latency 137782.763427 # average overall miss latency
326 system.iocache.overall_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency
327 system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
328 system.iocache.overall_hits 0 # number of overall hits
329 system.iocache.overall_miss_latency 5748985804 # number of overall miss cycles
330 system.iocache.overall_miss_rate 1 # miss rate for overall accesses
331 system.iocache.overall_misses 41725 # number of overall misses
332 system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
333 system.iocache.overall_mshr_miss_latency 3579140924 # number of overall MSHR miss cycles
334 system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
335 system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
336 system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
337 system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
338 system.iocache.replacements 41685 # number of replacements
339 system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
340 system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
341 system.iocache.tagsinuse 1.353399 # Cycle average of tags in use
342 system.iocache.total_refs 0 # Total number of references to valid blocks.
343 system.iocache.warmup_cycle 1762299470000 # Cycle when the warmup percentage was hit.
344 system.iocache.writebacks 41512 # number of writebacks
345 system.l2c.ReadExReq_accesses 304636 # number of ReadExReq accesses(hits+misses)
346 system.l2c.ReadExReq_avg_miss_latency 52003.289171 # average ReadExReq miss latency
347 system.l2c.ReadExReq_avg_mshr_miss_latency 40003.289171 # average ReadExReq mshr miss latency
348 system.l2c.ReadExReq_miss_latency 15842074000 # number of ReadExReq miss cycles
349 system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
350 system.l2c.ReadExReq_misses 304636 # number of ReadExReq misses
351 system.l2c.ReadExReq_mshr_miss_latency 12186442000 # number of ReadExReq MSHR miss cycles
352 system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
353 system.l2c.ReadExReq_mshr_misses 304636 # number of ReadExReq MSHR misses
354 system.l2c.ReadReq_accesses 2018564 # number of ReadReq accesses(hits+misses)
355 system.l2c.ReadReq_avg_miss_latency 52016.377161 # average ReadReq miss latency
356 system.l2c.ReadReq_avg_mshr_miss_latency 40016.359280 # average ReadReq mshr miss latency
357 system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
358 system.l2c.ReadReq_hits 1710971 # number of ReadReq hits
359 system.l2c.ReadReq_miss_latency 15999873500 # number of ReadReq miss cycles
360 system.l2c.ReadReq_miss_rate 0.152382 # miss rate for ReadReq accesses
361 system.l2c.ReadReq_misses 307593 # number of ReadReq misses
362 system.l2c.ReadReq_mshr_miss_latency 12308752000 # number of ReadReq MSHR miss cycles
363 system.l2c.ReadReq_mshr_miss_rate 0.152382 # mshr miss rate for ReadReq accesses
364 system.l2c.ReadReq_mshr_misses 307593 # number of ReadReq MSHR misses
365 system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles
366 system.l2c.UpgradeReq_accesses 126223 # number of UpgradeReq accesses(hits+misses)
367 system.l2c.UpgradeReq_avg_miss_latency 52001.810288 # average UpgradeReq miss latency
368 system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.910175 # average UpgradeReq mshr miss latency
369 system.l2c.UpgradeReq_miss_latency 6563824500 # number of UpgradeReq miss cycles
370 system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
371 system.l2c.UpgradeReq_misses 126223 # number of UpgradeReq misses
372 system.l2c.UpgradeReq_mshr_miss_latency 5049666000 # number of UpgradeReq MSHR miss cycles
373 system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
374 system.l2c.UpgradeReq_mshr_misses 126223 # number of UpgradeReq MSHR misses
375 system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
376 system.l2c.WriteReq_mshr_uncacheable_latency 1085299500 # number of WriteReq MSHR uncacheable cycles
377 system.l2c.Writeback_accesses 430459 # number of Writeback accesses(hits+misses)
378 system.l2c.Writeback_hits 430459 # number of Writeback hits
379 system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
380 system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
381 system.l2c.avg_refs 4.436562 # Average number of references to valid blocks.
382 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
383 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
384 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
385 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
386 system.l2c.cache_copies 0 # number of cache copies performed
387 system.l2c.demand_accesses 2323200 # number of demand (read+write) accesses
388 system.l2c.demand_avg_miss_latency 52009.864773 # average overall miss latency
389 system.l2c.demand_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency
390 system.l2c.demand_hits 1710971 # number of demand (read+write) hits
391 system.l2c.demand_miss_latency 31841947500 # number of demand (read+write) miss cycles
392 system.l2c.demand_miss_rate 0.263528 # miss rate for demand accesses
393 system.l2c.demand_misses 612229 # number of demand (read+write) misses
394 system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
395 system.l2c.demand_mshr_miss_latency 24495194000 # number of demand (read+write) MSHR miss cycles
396 system.l2c.demand_mshr_miss_rate 0.263528 # mshr miss rate for demand accesses
397 system.l2c.demand_mshr_misses 612229 # number of demand (read+write) MSHR misses
398 system.l2c.fast_writes 0 # number of fast writes performed
399 system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
400 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
401 system.l2c.overall_accesses 2323200 # number of overall (read+write) accesses
402 system.l2c.overall_avg_miss_latency 52009.864773 # average overall miss latency
403 system.l2c.overall_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency
404 system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
405 system.l2c.overall_hits 1710971 # number of overall hits
406 system.l2c.overall_miss_latency 31841947500 # number of overall miss cycles
407 system.l2c.overall_miss_rate 0.263528 # miss rate for overall accesses
408 system.l2c.overall_misses 612229 # number of overall misses
409 system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
410 system.l2c.overall_mshr_miss_latency 24495194000 # number of overall MSHR miss cycles
411 system.l2c.overall_mshr_miss_rate 0.263528 # mshr miss rate for overall accesses
412 system.l2c.overall_mshr_misses 612229 # number of overall MSHR misses
413 system.l2c.overall_mshr_uncacheable_latency 1857972500 # number of overall MSHR uncacheable cycles
414 system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
415 system.l2c.replacements 394928 # number of replacements
416 system.l2c.sampled_refs 425903 # Sample count of references to valid blocks.
417 system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
418 system.l2c.tagsinuse 30591.543942 # Cycle average of tags in use
419 system.l2c.total_refs 1889545 # Total number of references to valid blocks.
420 system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit.
421 system.l2c.writebacks 119060 # number of writebacks
422 system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
423 system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
424 system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
425 system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
426 system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
427 system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
428 system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
429 system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
430 system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
431 system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
432 system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
433 system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
434 system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
435 system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
436 system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
437 system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
438 system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
439 system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
440 system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
441 system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
442 system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
443 system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
444 system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
445 system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
446 system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
447 system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
448 system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
449 system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
450 system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
451 system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
452 system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
454 ---------- End Simulation Statistics ----------
projects / gem5.git / blob