2 ---------- Begin Simulation Statistics ----------
3 host_inst_rate 1925695 # Simulator instruction rate (inst/s)
4 host_mem_usage 381972 # Number of bytes of host memory used
5 host_seconds 27.06 # Real time elapsed on the host
6 host_tick_rate 975977117 # Simulator tick rate (ticks/s)
7 sim_freq 1000000000000 # Frequency of simulated ticks
8 sim_insts 52100192 # Number of instructions simulated
9 sim_seconds 0.026406 # Number of seconds simulated
10 sim_ticks 26405524500 # Number of ticks simulated
11 system.cpu.dcache.LoadLockedReq_accesses::0 100461 # number of LoadLockedReq accesses(hits+misses)
12 system.cpu.dcache.LoadLockedReq_accesses::total 100461 # number of LoadLockedReq accesses(hits+misses)
13 system.cpu.dcache.LoadLockedReq_hits::0 95296 # number of LoadLockedReq hits
14 system.cpu.dcache.LoadLockedReq_hits::total 95296 # number of LoadLockedReq hits
15 system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051413 # miss rate for LoadLockedReq accesses
16 system.cpu.dcache.LoadLockedReq_misses::0 5165 # number of LoadLockedReq misses
17 system.cpu.dcache.LoadLockedReq_misses::total 5165 # number of LoadLockedReq misses
18 system.cpu.dcache.ReadReq_accesses::0 7831528 # number of ReadReq accesses(hits+misses)
19 system.cpu.dcache.ReadReq_accesses::total 7831528 # number of ReadReq accesses(hits+misses)
20 system.cpu.dcache.ReadReq_hits::0 7594963 # number of ReadReq hits
21 system.cpu.dcache.ReadReq_hits::total 7594963 # number of ReadReq hits
22 system.cpu.dcache.ReadReq_miss_rate::0 0.030207 # miss rate for ReadReq accesses
23 system.cpu.dcache.ReadReq_misses::0 236565 # number of ReadReq misses
24 system.cpu.dcache.ReadReq_misses::total 236565 # number of ReadReq misses
25 system.cpu.dcache.StoreCondReq_accesses::0 100460 # number of StoreCondReq accesses(hits+misses)
26 system.cpu.dcache.StoreCondReq_accesses::total 100460 # number of StoreCondReq accesses(hits+misses)
27 system.cpu.dcache.StoreCondReq_hits::0 100460 # number of StoreCondReq hits
28 system.cpu.dcache.StoreCondReq_hits::total 100460 # number of StoreCondReq hits
29 system.cpu.dcache.WriteReq_accesses::0 6676897 # number of WriteReq accesses(hits+misses)
30 system.cpu.dcache.WriteReq_accesses::total 6676897 # number of WriteReq accesses(hits+misses)
31 system.cpu.dcache.WriteReq_hits::0 6504656 # number of WriteReq hits
32 system.cpu.dcache.WriteReq_hits::total 6504656 # number of WriteReq hits
33 system.cpu.dcache.WriteReq_miss_rate::0 0.025797 # miss rate for WriteReq accesses
34 system.cpu.dcache.WriteReq_misses::0 172241 # number of WriteReq misses
35 system.cpu.dcache.WriteReq_misses::total 172241 # number of WriteReq misses
36 system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
37 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
38 system.cpu.dcache.avg_refs 34.690601 # Average number of references to valid blocks.
39 system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
40 system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
41 system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
42 system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
43 system.cpu.dcache.cache_copies 0 # number of cache copies performed
44 system.cpu.dcache.demand_accesses::0 14508425 # number of demand (read+write) accesses
45 system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
46 system.cpu.dcache.demand_accesses::total 14508425 # number of demand (read+write) accesses
47 system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
48 system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
49 system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
50 system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
51 system.cpu.dcache.demand_hits::0 14099619 # number of demand (read+write) hits
52 system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
53 system.cpu.dcache.demand_hits::total 14099619 # number of demand (read+write) hits
54 system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
55 system.cpu.dcache.demand_miss_rate::0 0.028177 # miss rate for demand accesses
56 system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
57 system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
58 system.cpu.dcache.demand_misses::0 408806 # number of demand (read+write) misses
59 system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
60 system.cpu.dcache.demand_misses::total 408806 # number of demand (read+write) misses
61 system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
62 system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
63 system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
64 system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
65 system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
66 system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
67 system.cpu.dcache.fast_writes 0 # number of fast writes performed
68 system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
69 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
70 system.cpu.dcache.occ_%::0 0.999487 # Average percentage of cache occupancy
71 system.cpu.dcache.occ_blocks::0 511.737186 # Average occupied blocks per context
72 system.cpu.dcache.overall_accesses::0 14508425 # number of overall (read+write) accesses
73 system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
74 system.cpu.dcache.overall_accesses::total 14508425 # number of overall (read+write) accesses
75 system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
76 system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
77 system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
78 system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
79 system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
80 system.cpu.dcache.overall_hits::0 14099619 # number of overall hits
81 system.cpu.dcache.overall_hits::1 0 # number of overall hits
82 system.cpu.dcache.overall_hits::total 14099619 # number of overall hits
83 system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
84 system.cpu.dcache.overall_miss_rate::0 0.028177 # miss rate for overall accesses
85 system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
86 system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
87 system.cpu.dcache.overall_misses::0 408806 # number of overall misses
88 system.cpu.dcache.overall_misses::1 0 # number of overall misses
89 system.cpu.dcache.overall_misses::total 408806 # number of overall misses
90 system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
91 system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
92 system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
93 system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
94 system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
95 system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
96 system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
97 system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
98 system.cpu.dcache.replacements 411623 # number of replacements
99 system.cpu.dcache.sampled_refs 412135 # Sample count of references to valid blocks.
100 system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
101 system.cpu.dcache.tagsinuse 511.737186 # Cycle average of tags in use
102 system.cpu.dcache.total_refs 14297211 # Total number of references to valid blocks.
103 system.cpu.dcache.warmup_cycle 21760500 # Cycle when the warmup percentage was hit.
104 system.cpu.dcache.writebacks 381909 # number of writebacks
105 system.cpu.dtb.accesses 15532989 # DTB accesses
106 system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
107 system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
108 system.cpu.dtb.flush_entries 2238 # Number of entries that have been flushed from TLB
109 system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
110 system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
111 system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
112 system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
113 system.cpu.dtb.hits 15527459 # DTB hits
114 system.cpu.dtb.inst_accesses 0 # ITB inst accesses
115 system.cpu.dtb.inst_hits 0 # ITB inst hits
116 system.cpu.dtb.inst_misses 0 # ITB inst misses
117 system.cpu.dtb.misses 5530 # DTB misses
118 system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions
119 system.cpu.dtb.prefetch_faults 767 # Number of TLB faults due to prefetch
120 system.cpu.dtb.read_accesses 8743878 # DTB read accesses
121 system.cpu.dtb.read_hits 8739345 # DTB read hits
122 system.cpu.dtb.read_misses 4533 # DTB read misses
123 system.cpu.dtb.write_accesses 6789111 # DTB write accesses
124 system.cpu.dtb.write_hits 6788114 # DTB write hits
125 system.cpu.dtb.write_misses 997 # DTB write misses
126 system.cpu.icache.ReadReq_accesses::0 41566870 # number of ReadReq accesses(hits+misses)
127 system.cpu.icache.ReadReq_accesses::total 41566870 # number of ReadReq accesses(hits+misses)
128 system.cpu.icache.ReadReq_hits::0 41133444 # number of ReadReq hits
129 system.cpu.icache.ReadReq_hits::total 41133444 # number of ReadReq hits
130 system.cpu.icache.ReadReq_miss_rate::0 0.010427 # miss rate for ReadReq accesses
131 system.cpu.icache.ReadReq_misses::0 433426 # number of ReadReq misses
132 system.cpu.icache.ReadReq_misses::total 433426 # number of ReadReq misses
133 system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
134 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
135 system.cpu.icache.avg_refs 94.903257 # Average number of references to valid blocks.
136 system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
137 system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
138 system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
139 system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
140 system.cpu.icache.cache_copies 0 # number of cache copies performed
141 system.cpu.icache.demand_accesses::0 41566870 # number of demand (read+write) accesses
142 system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
143 system.cpu.icache.demand_accesses::total 41566870 # number of demand (read+write) accesses
144 system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency
145 system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
146 system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency
147 system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
148 system.cpu.icache.demand_hits::0 41133444 # number of demand (read+write) hits
149 system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
150 system.cpu.icache.demand_hits::total 41133444 # number of demand (read+write) hits
151 system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
152 system.cpu.icache.demand_miss_rate::0 0.010427 # miss rate for demand accesses
153 system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
154 system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
155 system.cpu.icache.demand_misses::0 433426 # number of demand (read+write) misses
156 system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
157 system.cpu.icache.demand_misses::total 433426 # number of demand (read+write) misses
158 system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
159 system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
160 system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
161 system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
162 system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
163 system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
164 system.cpu.icache.fast_writes 0 # number of fast writes performed
165 system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
166 system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
167 system.cpu.icache.occ_%::0 0.930522 # Average percentage of cache occupancy
168 system.cpu.icache.occ_blocks::0 476.427204 # Average occupied blocks per context
169 system.cpu.icache.overall_accesses::0 41566870 # number of overall (read+write) accesses
170 system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
171 system.cpu.icache.overall_accesses::total 41566870 # number of overall (read+write) accesses
172 system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency
173 system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
174 system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency
175 system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
176 system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
177 system.cpu.icache.overall_hits::0 41133444 # number of overall hits
178 system.cpu.icache.overall_hits::1 0 # number of overall hits
179 system.cpu.icache.overall_hits::total 41133444 # number of overall hits
180 system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
181 system.cpu.icache.overall_miss_rate::0 0.010427 # miss rate for overall accesses
182 system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
183 system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
184 system.cpu.icache.overall_misses::0 433426 # number of overall misses
185 system.cpu.icache.overall_misses::1 0 # number of overall misses
186 system.cpu.icache.overall_misses::total 433426 # number of overall misses
187 system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
188 system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
189 system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
190 system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
191 system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
192 system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses
193 system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
194 system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
195 system.cpu.icache.replacements 432913 # number of replacements
196 system.cpu.icache.sampled_refs 433425 # Sample count of references to valid blocks.
197 system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
198 system.cpu.icache.tagsinuse 476.427204 # Cycle average of tags in use
199 system.cpu.icache.total_refs 41133444 # Total number of references to valid blocks.
200 system.cpu.icache.warmup_cycle 4575402000 # Cycle when the warmup percentage was hit.
201 system.cpu.icache.writebacks 33681 # number of writebacks
202 system.cpu.idle_fraction 0 # Percentage of idle cycles
203 system.cpu.itb.accesses 41567997 # DTB accesses
204 system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
205 system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
206 system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB
207 system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
208 system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
209 system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
210 system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
211 system.cpu.itb.hits 41565169 # DTB hits
212 system.cpu.itb.inst_accesses 41567997 # ITB inst accesses
213 system.cpu.itb.inst_hits 41565169 # ITB inst hits
214 system.cpu.itb.inst_misses 2828 # ITB inst misses
215 system.cpu.itb.misses 2828 # DTB misses
216 system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
217 system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
218 system.cpu.itb.read_accesses 0 # DTB read accesses
219 system.cpu.itb.read_hits 0 # DTB read hits
220 system.cpu.itb.read_misses 0 # DTB read misses
221 system.cpu.itb.write_accesses 0 # DTB write accesses
222 system.cpu.itb.write_hits 0 # DTB write hits
223 system.cpu.itb.write_misses 0 # DTB write misses
224 system.cpu.kern.inst.arm 0 # number of arm instructions executed
225 system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
226 system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
227 system.cpu.numCycles 52811050 # number of cpu cycles simulated
228 system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
229 system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
230 system.cpu.num_busy_cycles 52811050 # Number of busy cycles
231 system.cpu.num_conditional_control_insts 7028967 # number of instructions that are conditional controls
232 system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses
233 system.cpu.num_fp_insts 6058 # number of float instructions
234 system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read
235 system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written
236 system.cpu.num_func_calls 1109362 # number of times a function call or return occured
237 system.cpu.num_idle_cycles 0 # Number of idle cycles
238 system.cpu.num_insts 52100192 # Number of instructions executed
239 system.cpu.num_int_alu_accesses 42511691 # Number of integer alu accesses
240 system.cpu.num_int_insts 42511691 # number of integer instructions
241 system.cpu.num_int_register_reads 131109932 # number of times the integer registers were read
242 system.cpu.num_int_register_writes 34554918 # number of times the integer registers were written
243 system.cpu.num_load_insts 9209160 # Number of load instructions
244 system.cpu.num_mem_refs 16296226 # number of memory refs
245 system.cpu.num_store_insts 7087066 # Number of store instructions
246 system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
247 system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
248 system.iocache.avg_refs no_value # Average number of references to valid blocks.
249 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
250 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
251 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
252 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
253 system.iocache.cache_copies 0 # number of cache copies performed
254 system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
255 system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
256 system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
257 system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
258 system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
259 system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
260 system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
261 system.iocache.demand_hits::0 0 # number of demand (read+write) hits
262 system.iocache.demand_hits::1 0 # number of demand (read+write) hits
263 system.iocache.demand_hits::total 0 # number of demand (read+write) hits
264 system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
265 system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
266 system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
267 system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
268 system.iocache.demand_misses::0 0 # number of demand (read+write) misses
269 system.iocache.demand_misses::1 0 # number of demand (read+write) misses
270 system.iocache.demand_misses::total 0 # number of demand (read+write) misses
271 system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
272 system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
273 system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
274 system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
275 system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
276 system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
277 system.iocache.fast_writes 0 # number of fast writes performed
278 system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
279 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
280 system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
281 system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
282 system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
283 system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
284 system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
285 system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
286 system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
287 system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
288 system.iocache.overall_hits::0 0 # number of overall hits
289 system.iocache.overall_hits::1 0 # number of overall hits
290 system.iocache.overall_hits::total 0 # number of overall hits
291 system.iocache.overall_miss_latency 0 # number of overall miss cycles
292 system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
293 system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
294 system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
295 system.iocache.overall_misses::0 0 # number of overall misses
296 system.iocache.overall_misses::1 0 # number of overall misses
297 system.iocache.overall_misses::total 0 # number of overall misses
298 system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
299 system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
300 system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
301 system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
302 system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
303 system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
304 system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
305 system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
306 system.iocache.replacements 0 # number of replacements
307 system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
308 system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
309 system.iocache.tagsinuse 0 # Cycle average of tags in use
310 system.iocache.total_refs 0 # Total number of references to valid blocks.
311 system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
312 system.iocache.writebacks 0 # number of writebacks
313 system.l2c.ReadExReq_accesses::0 170405 # number of ReadExReq accesses(hits+misses)
314 system.l2c.ReadExReq_accesses::total 170405 # number of ReadExReq accesses(hits+misses)
315 system.l2c.ReadExReq_hits::0 60553 # number of ReadExReq hits
316 system.l2c.ReadExReq_hits::total 60553 # number of ReadExReq hits
317 system.l2c.ReadExReq_miss_rate::0 0.644652 # miss rate for ReadExReq accesses
318 system.l2c.ReadExReq_misses::0 109852 # number of ReadExReq misses
319 system.l2c.ReadExReq_misses::total 109852 # number of ReadExReq misses
320 system.l2c.ReadReq_accesses::0 673057 # number of ReadReq accesses(hits+misses)
321 system.l2c.ReadReq_accesses::1 6142 # number of ReadReq accesses(hits+misses)
322 system.l2c.ReadReq_accesses::total 679199 # number of ReadReq accesses(hits+misses)
323 system.l2c.ReadReq_hits::0 651904 # number of ReadReq hits
324 system.l2c.ReadReq_hits::1 6117 # number of ReadReq hits
325 system.l2c.ReadReq_hits::total 658021 # number of ReadReq hits
326 system.l2c.ReadReq_miss_rate::0 0.031428 # miss rate for ReadReq accesses
327 system.l2c.ReadReq_miss_rate::1 0.004070 # miss rate for ReadReq accesses
328 system.l2c.ReadReq_miss_rate::total 0.035499 # miss rate for ReadReq accesses
329 system.l2c.ReadReq_misses::0 21153 # number of ReadReq misses
330 system.l2c.ReadReq_misses::1 25 # number of ReadReq misses
331 system.l2c.ReadReq_misses::total 21178 # number of ReadReq misses
332 system.l2c.UpgradeReq_accesses::0 1836 # number of UpgradeReq accesses(hits+misses)
333 system.l2c.UpgradeReq_accesses::total 1836 # number of UpgradeReq accesses(hits+misses)
334 system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits
335 system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits
336 system.l2c.UpgradeReq_miss_rate::0 0.990741 # miss rate for UpgradeReq accesses
337 system.l2c.UpgradeReq_misses::0 1819 # number of UpgradeReq misses
338 system.l2c.UpgradeReq_misses::total 1819 # number of UpgradeReq misses
339 system.l2c.Writeback_accesses::0 415590 # number of Writeback accesses(hits+misses)
340 system.l2c.Writeback_accesses::total 415590 # number of Writeback accesses(hits+misses)
341 system.l2c.Writeback_hits::0 415590 # number of Writeback hits
342 system.l2c.Writeback_hits::total 415590 # number of Writeback hits
343 system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
344 system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
345 system.l2c.avg_refs 6.746349 # Average number of references to valid blocks.
346 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
347 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
348 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
349 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
350 system.l2c.cache_copies 0 # number of cache copies performed
351 system.l2c.demand_accesses::0 843462 # number of demand (read+write) accesses
352 system.l2c.demand_accesses::1 6142 # number of demand (read+write) accesses
353 system.l2c.demand_accesses::total 849604 # number of demand (read+write) accesses
354 system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
355 system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
356 system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
357 system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
358 system.l2c.demand_hits::0 712457 # number of demand (read+write) hits
359 system.l2c.demand_hits::1 6117 # number of demand (read+write) hits
360 system.l2c.demand_hits::total 718574 # number of demand (read+write) hits
361 system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
362 system.l2c.demand_miss_rate::0 0.155318 # miss rate for demand accesses
363 system.l2c.demand_miss_rate::1 0.004070 # miss rate for demand accesses
364 system.l2c.demand_miss_rate::total 0.159389 # miss rate for demand accesses
365 system.l2c.demand_misses::0 131005 # number of demand (read+write) misses
366 system.l2c.demand_misses::1 25 # number of demand (read+write) misses
367 system.l2c.demand_misses::total 131030 # number of demand (read+write) misses
368 system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
369 system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
370 system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
371 system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
372 system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
373 system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
374 system.l2c.fast_writes 0 # number of fast writes performed
375 system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
376 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
377 system.l2c.occ_%::0 0.076949 # Average percentage of cache occupancy
378 system.l2c.occ_%::1 0.477056 # Average percentage of cache occupancy
379 system.l2c.occ_blocks::0 5042.918302 # Average occupied blocks per context
380 system.l2c.occ_blocks::1 31264.310783 # Average occupied blocks per context
381 system.l2c.overall_accesses::0 843462 # number of overall (read+write) accesses
382 system.l2c.overall_accesses::1 6142 # number of overall (read+write) accesses
383 system.l2c.overall_accesses::total 849604 # number of overall (read+write) accesses
384 system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
385 system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
386 system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
387 system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
388 system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
389 system.l2c.overall_hits::0 712457 # number of overall hits
390 system.l2c.overall_hits::1 6117 # number of overall hits
391 system.l2c.overall_hits::total 718574 # number of overall hits
392 system.l2c.overall_miss_latency 0 # number of overall miss cycles
393 system.l2c.overall_miss_rate::0 0.155318 # miss rate for overall accesses
394 system.l2c.overall_miss_rate::1 0.004070 # miss rate for overall accesses
395 system.l2c.overall_miss_rate::total 0.159389 # miss rate for overall accesses
396 system.l2c.overall_misses::0 131005 # number of overall misses
397 system.l2c.overall_misses::1 25 # number of overall misses
398 system.l2c.overall_misses::total 131030 # number of overall misses
399 system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
400 system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
401 system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
402 system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
403 system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
404 system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
405 system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
406 system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
407 system.l2c.replacements 97025 # number of replacements
408 system.l2c.sampled_refs 129753 # Sample count of references to valid blocks.
409 system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
410 system.l2c.tagsinuse 36307.229085 # Cycle average of tags in use
411 system.l2c.total_refs 875359 # Total number of references to valid blocks.
412 system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
413 system.l2c.writebacks 90930 # number of writebacks
415 ---------- End Simulation Statistics ----------
projects / gem5.git / blob