2 ---------- Begin Simulation Statistics ----------
3 sim_seconds 2.669611 # Number of seconds simulated
4 sim_ticks 2669611225000 # Number of ticks simulated
5 final_tick 2669611225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6 sim_freq 1000000000000 # Frequency of simulated ticks
7 host_inst_rate 842154 # Simulator instruction rate (inst/s)
8 host_tick_rate 28671225175 # Simulator tick rate (ticks/s)
9 host_mem_usage 380676 # Number of bytes of host memory used
10 host_seconds 93.11 # Real time elapsed on the host
11 sim_insts 78413959 # Number of instructions simulated
12 system.nvmem.bytes_read 68 # Number of bytes read from this memory
13 system.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory
14 system.nvmem.bytes_written 0 # Number of bytes written to this memory
15 system.nvmem.num_reads 17 # Number of read requests responded to by this memory
16 system.nvmem.num_writes 0 # Number of write requests responded to by this memory
17 system.nvmem.num_other 0 # Number of other requests responded to by this memory
18 system.nvmem.bw_read 25 # Total read bandwidth from this memory (bytes/s)
19 system.nvmem.bw_inst_read 25 # Instruction read bandwidth from this memory (bytes/s)
20 system.nvmem.bw_total 25 # Total bandwidth to/from this memory (bytes/s)
21 system.physmem.bytes_read 134334820 # Number of bytes read from this memory
22 system.physmem.bytes_inst_read 1003520 # Number of instructions bytes read from this memory
23 system.physmem.bytes_written 10194256 # Number of bytes written to this memory
24 system.physmem.num_reads 15523876 # Number of read requests responded to by this memory
25 system.physmem.num_writes 869239 # Number of write requests responded to by this memory
26 system.physmem.num_other 0 # Number of other requests responded to by this memory
27 system.physmem.bw_read 50319994 # Total read bandwidth from this memory (bytes/s)
28 system.physmem.bw_inst_read 375905 # Instruction read bandwidth from this memory (bytes/s)
29 system.physmem.bw_write 3818629 # Write bandwidth from this memory (bytes/s)
30 system.physmem.bw_total 54138623 # Total bandwidth to/from this memory (bytes/s)
31 system.l2c.replacements 127749 # number of replacements
32 system.l2c.tagsinuse 26172.513439 # Cycle average of tags in use
33 system.l2c.total_refs 1540412 # Total number of references to valid blocks.
34 system.l2c.sampled_refs 157158 # Sample count of references to valid blocks.
35 system.l2c.avg_refs 9.801677 # Average number of references to valid blocks.
36 system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
37 system.l2c.occ_blocks::0 6351.465954 # Average occupied blocks per context
38 system.l2c.occ_blocks::1 4614.904109 # Average occupied blocks per context
39 system.l2c.occ_blocks::2 15206.143377 # Average occupied blocks per context
40 system.l2c.occ_percent::0 0.096916 # Average percentage of cache occupancy
41 system.l2c.occ_percent::1 0.070418 # Average percentage of cache occupancy
42 system.l2c.occ_percent::2 0.232027 # Average percentage of cache occupancy
43 system.l2c.ReadReq_hits::0 562859 # number of ReadReq hits
44 system.l2c.ReadReq_hits::1 656143 # number of ReadReq hits
45 system.l2c.ReadReq_hits::2 11798 # number of ReadReq hits
46 system.l2c.ReadReq_hits::total 1230800 # number of ReadReq hits
47 system.l2c.Writeback_hits::0 589400 # number of Writeback hits
48 system.l2c.Writeback_hits::total 589400 # number of Writeback hits
49 system.l2c.UpgradeReq_hits::0 1143 # number of UpgradeReq hits
50 system.l2c.UpgradeReq_hits::1 692 # number of UpgradeReq hits
51 system.l2c.UpgradeReq_hits::total 1835 # number of UpgradeReq hits
52 system.l2c.SCUpgradeReq_hits::0 168 # number of SCUpgradeReq hits
53 system.l2c.SCUpgradeReq_hits::1 186 # number of SCUpgradeReq hits
54 system.l2c.SCUpgradeReq_hits::total 354 # number of SCUpgradeReq hits
55 system.l2c.ReadExReq_hits::0 42506 # number of ReadExReq hits
56 system.l2c.ReadExReq_hits::1 58554 # number of ReadExReq hits
57 system.l2c.ReadExReq_hits::total 101060 # number of ReadExReq hits
58 system.l2c.demand_hits::0 605365 # number of demand (read+write) hits
59 system.l2c.demand_hits::1 714697 # number of demand (read+write) hits
60 system.l2c.demand_hits::2 11798 # number of demand (read+write) hits
61 system.l2c.demand_hits::total 1331860 # number of demand (read+write) hits
62 system.l2c.overall_hits::0 605365 # number of overall hits
63 system.l2c.overall_hits::1 714697 # number of overall hits
64 system.l2c.overall_hits::2 11798 # number of overall hits
65 system.l2c.overall_hits::total 1331860 # number of overall hits
66 system.l2c.ReadReq_misses::0 18655 # number of ReadReq misses
67 system.l2c.ReadReq_misses::1 16034 # number of ReadReq misses
68 system.l2c.ReadReq_misses::2 50 # number of ReadReq misses
69 system.l2c.ReadReq_misses::total 34739 # number of ReadReq misses
70 system.l2c.UpgradeReq_misses::0 3515 # number of UpgradeReq misses
71 system.l2c.UpgradeReq_misses::1 5223 # number of UpgradeReq misses
72 system.l2c.UpgradeReq_misses::total 8738 # number of UpgradeReq misses
73 system.l2c.SCUpgradeReq_misses::0 546 # number of SCUpgradeReq misses
74 system.l2c.SCUpgradeReq_misses::1 614 # number of SCUpgradeReq misses
75 system.l2c.SCUpgradeReq_misses::total 1160 # number of SCUpgradeReq misses
76 system.l2c.ReadExReq_misses::0 97324 # number of ReadExReq misses
77 system.l2c.ReadExReq_misses::1 51524 # number of ReadExReq misses
78 system.l2c.ReadExReq_misses::total 148848 # number of ReadExReq misses
79 system.l2c.demand_misses::0 115979 # number of demand (read+write) misses
80 system.l2c.demand_misses::1 67558 # number of demand (read+write) misses
81 system.l2c.demand_misses::2 50 # number of demand (read+write) misses
82 system.l2c.demand_misses::total 183587 # number of demand (read+write) misses
83 system.l2c.overall_misses::0 115979 # number of overall misses
84 system.l2c.overall_misses::1 67558 # number of overall misses
85 system.l2c.overall_misses::2 50 # number of overall misses
86 system.l2c.overall_misses::total 183587 # number of overall misses
87 system.l2c.ReadReq_miss_latency 1812504500 # number of ReadReq miss cycles
88 system.l2c.UpgradeReq_miss_latency 56471000 # number of UpgradeReq miss cycles
89 system.l2c.SCUpgradeReq_miss_latency 6300000 # number of SCUpgradeReq miss cycles
90 system.l2c.ReadExReq_miss_latency 7751543000 # number of ReadExReq miss cycles
91 system.l2c.demand_miss_latency 9564047500 # number of demand (read+write) miss cycles
92 system.l2c.overall_miss_latency 9564047500 # number of overall miss cycles
93 system.l2c.ReadReq_accesses::0 581514 # number of ReadReq accesses(hits+misses)
94 system.l2c.ReadReq_accesses::1 672177 # number of ReadReq accesses(hits+misses)
95 system.l2c.ReadReq_accesses::2 11848 # number of ReadReq accesses(hits+misses)
96 system.l2c.ReadReq_accesses::total 1265539 # number of ReadReq accesses(hits+misses)
97 system.l2c.Writeback_accesses::0 589400 # number of Writeback accesses(hits+misses)
98 system.l2c.Writeback_accesses::total 589400 # number of Writeback accesses(hits+misses)
99 system.l2c.UpgradeReq_accesses::0 4658 # number of UpgradeReq accesses(hits+misses)
100 system.l2c.UpgradeReq_accesses::1 5915 # number of UpgradeReq accesses(hits+misses)
101 system.l2c.UpgradeReq_accesses::total 10573 # number of UpgradeReq accesses(hits+misses)
102 system.l2c.SCUpgradeReq_accesses::0 714 # number of SCUpgradeReq accesses(hits+misses)
103 system.l2c.SCUpgradeReq_accesses::1 800 # number of SCUpgradeReq accesses(hits+misses)
104 system.l2c.SCUpgradeReq_accesses::total 1514 # number of SCUpgradeReq accesses(hits+misses)
105 system.l2c.ReadExReq_accesses::0 139830 # number of ReadExReq accesses(hits+misses)
106 system.l2c.ReadExReq_accesses::1 110078 # number of ReadExReq accesses(hits+misses)
107 system.l2c.ReadExReq_accesses::total 249908 # number of ReadExReq accesses(hits+misses)
108 system.l2c.demand_accesses::0 721344 # number of demand (read+write) accesses
109 system.l2c.demand_accesses::1 782255 # number of demand (read+write) accesses
110 system.l2c.demand_accesses::2 11848 # number of demand (read+write) accesses
111 system.l2c.demand_accesses::total 1515447 # number of demand (read+write) accesses
112 system.l2c.overall_accesses::0 721344 # number of overall (read+write) accesses
113 system.l2c.overall_accesses::1 782255 # number of overall (read+write) accesses
114 system.l2c.overall_accesses::2 11848 # number of overall (read+write) accesses
115 system.l2c.overall_accesses::total 1515447 # number of overall (read+write) accesses
116 system.l2c.ReadReq_miss_rate::0 0.032080 # miss rate for ReadReq accesses
117 system.l2c.ReadReq_miss_rate::1 0.023854 # miss rate for ReadReq accesses
118 system.l2c.ReadReq_miss_rate::2 0.004220 # miss rate for ReadReq accesses
119 system.l2c.ReadReq_miss_rate::total 0.060154 # miss rate for ReadReq accesses
120 system.l2c.UpgradeReq_miss_rate::0 0.754616 # miss rate for UpgradeReq accesses
121 system.l2c.UpgradeReq_miss_rate::1 0.883009 # miss rate for UpgradeReq accesses
122 system.l2c.SCUpgradeReq_miss_rate::0 0.764706 # miss rate for SCUpgradeReq accesses
123 system.l2c.SCUpgradeReq_miss_rate::1 0.767500 # miss rate for SCUpgradeReq accesses
124 system.l2c.ReadExReq_miss_rate::0 0.696017 # miss rate for ReadExReq accesses
125 system.l2c.ReadExReq_miss_rate::1 0.468068 # miss rate for ReadExReq accesses
126 system.l2c.demand_miss_rate::0 0.160782 # miss rate for demand accesses
127 system.l2c.demand_miss_rate::1 0.086363 # miss rate for demand accesses
128 system.l2c.demand_miss_rate::2 0.004220 # miss rate for demand accesses
129 system.l2c.demand_miss_rate::total 0.251365 # miss rate for demand accesses
130 system.l2c.overall_miss_rate::0 0.160782 # miss rate for overall accesses
131 system.l2c.overall_miss_rate::1 0.086363 # miss rate for overall accesses
132 system.l2c.overall_miss_rate::2 0.004220 # miss rate for overall accesses
133 system.l2c.overall_miss_rate::total 0.251365 # miss rate for overall accesses
134 system.l2c.ReadReq_avg_miss_latency::0 97159.179845 # average ReadReq miss latency
135 system.l2c.ReadReq_avg_miss_latency::1 113041.318448 # average ReadReq miss latency
136 system.l2c.ReadReq_avg_miss_latency::2 36250090 # average ReadReq miss latency
137 system.l2c.ReadReq_avg_miss_latency::total 36460290.498293 # average ReadReq miss latency
138 system.l2c.UpgradeReq_avg_miss_latency::0 16065.718350 # average UpgradeReq miss latency
139 system.l2c.UpgradeReq_avg_miss_latency::1 10811.985449 # average UpgradeReq miss latency
140 system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency
141 system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
142 system.l2c.SCUpgradeReq_avg_miss_latency::0 11538.461538 # average SCUpgradeReq miss latency
143 system.l2c.SCUpgradeReq_avg_miss_latency::1 10260.586319 # average SCUpgradeReq miss latency
144 system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency
145 system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency
146 system.l2c.ReadExReq_avg_miss_latency::0 79646.777773 # average ReadExReq miss latency
147 system.l2c.ReadExReq_avg_miss_latency::1 150445.287633 # average ReadExReq miss latency
148 system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency
149 system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
150 system.l2c.demand_avg_miss_latency::0 82463.614103 # average overall miss latency
151 system.l2c.demand_avg_miss_latency::1 141567.949022 # average overall miss latency
152 system.l2c.demand_avg_miss_latency::2 191280950 # average overall miss latency
153 system.l2c.demand_avg_miss_latency::total 191504981.563124 # average overall miss latency
154 system.l2c.overall_avg_miss_latency::0 82463.614103 # average overall miss latency
155 system.l2c.overall_avg_miss_latency::1 141567.949022 # average overall miss latency
156 system.l2c.overall_avg_miss_latency::2 191280950 # average overall miss latency
157 system.l2c.overall_avg_miss_latency::total 191504981.563124 # average overall miss latency
158 system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
159 system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
160 system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
161 system.l2c.blocked::no_targets 0 # number of cycles access was blocked
162 system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
163 system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
164 system.l2c.fast_writes 0 # number of fast writes performed
165 system.l2c.cache_copies 0 # number of cache copies performed
166 system.l2c.writebacks 111955 # number of writebacks
167 system.l2c.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits
168 system.l2c.demand_mshr_hits 9 # number of demand (read+write) MSHR hits
169 system.l2c.overall_mshr_hits 9 # number of overall MSHR hits
170 system.l2c.ReadReq_mshr_misses 34730 # number of ReadReq MSHR misses
171 system.l2c.UpgradeReq_mshr_misses 8738 # number of UpgradeReq MSHR misses
172 system.l2c.SCUpgradeReq_mshr_misses 1160 # number of SCUpgradeReq MSHR misses
173 system.l2c.ReadExReq_mshr_misses 148848 # number of ReadExReq MSHR misses
174 system.l2c.demand_mshr_misses 183578 # number of demand (read+write) MSHR misses
175 system.l2c.overall_mshr_misses 183578 # number of overall MSHR misses
176 system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
177 system.l2c.ReadReq_mshr_miss_latency 1395310000 # number of ReadReq MSHR miss cycles
178 system.l2c.UpgradeReq_mshr_miss_latency 350593500 # number of UpgradeReq MSHR miss cycles
179 system.l2c.SCUpgradeReq_mshr_miss_latency 46546000 # number of SCUpgradeReq MSHR miss cycles
180 system.l2c.ReadExReq_mshr_miss_latency 5965367000 # number of ReadExReq MSHR miss cycles
181 system.l2c.demand_mshr_miss_latency 7360677000 # number of demand (read+write) MSHR miss cycles
182 system.l2c.overall_mshr_miss_latency 7360677000 # number of overall MSHR miss cycles
183 system.l2c.ReadReq_mshr_uncacheable_latency 131926671000 # number of ReadReq MSHR uncacheable cycles
184 system.l2c.WriteReq_mshr_uncacheable_latency 31372379500 # number of WriteReq MSHR uncacheable cycles
185 system.l2c.overall_mshr_uncacheable_latency 163299050500 # number of overall MSHR uncacheable cycles
186 system.l2c.ReadReq_mshr_miss_rate::0 0.059723 # mshr miss rate for ReadReq accesses
187 system.l2c.ReadReq_mshr_miss_rate::1 0.051668 # mshr miss rate for ReadReq accesses
188 system.l2c.ReadReq_mshr_miss_rate::2 2.931296 # mshr miss rate for ReadReq accesses
189 system.l2c.ReadReq_mshr_miss_rate::total 3.042688 # mshr miss rate for ReadReq accesses
190 system.l2c.UpgradeReq_mshr_miss_rate::0 1.875912 # mshr miss rate for UpgradeReq accesses
191 system.l2c.UpgradeReq_mshr_miss_rate::1 1.477261 # mshr miss rate for UpgradeReq accesses
192 system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses
193 system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
194 system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.624650 # mshr miss rate for SCUpgradeReq accesses
195 system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.450000 # mshr miss rate for SCUpgradeReq accesses
196 system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses
197 system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
198 system.l2c.ReadExReq_mshr_miss_rate::0 1.064493 # mshr miss rate for ReadExReq accesses
199 system.l2c.ReadExReq_mshr_miss_rate::1 1.352205 # mshr miss rate for ReadExReq accesses
200 system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses
201 system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
202 system.l2c.demand_mshr_miss_rate::0 0.254494 # mshr miss rate for demand accesses
203 system.l2c.demand_mshr_miss_rate::1 0.234678 # mshr miss rate for demand accesses
204 system.l2c.demand_mshr_miss_rate::2 15.494429 # mshr miss rate for demand accesses
205 system.l2c.demand_mshr_miss_rate::total 15.983602 # mshr miss rate for demand accesses
206 system.l2c.overall_mshr_miss_rate::0 0.254494 # mshr miss rate for overall accesses
207 system.l2c.overall_mshr_miss_rate::1 0.234678 # mshr miss rate for overall accesses
208 system.l2c.overall_mshr_miss_rate::2 15.494429 # mshr miss rate for overall accesses
209 system.l2c.overall_mshr_miss_rate::total 15.983602 # mshr miss rate for overall accesses
210 system.l2c.ReadReq_avg_mshr_miss_latency 40175.928592 # average ReadReq mshr miss latency
211 system.l2c.UpgradeReq_avg_mshr_miss_latency 40122.854200 # average UpgradeReq mshr miss latency
212 system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40125.862069 # average SCUpgradeReq mshr miss latency
213 system.l2c.ReadExReq_avg_mshr_miss_latency 40076.903956 # average ReadExReq mshr miss latency
214 system.l2c.demand_avg_mshr_miss_latency 40095.637822 # average overall mshr miss latency
215 system.l2c.overall_avg_mshr_miss_latency 40095.637822 # average overall mshr miss latency
216 system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
217 system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
218 system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
219 system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
220 system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
221 system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
222 system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
223 system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
224 system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
225 system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
226 system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
227 system.cf0.dma_write_txs 0 # Number of DMA write transactions.
228 system.cpu0.dtb.inst_hits 0 # ITB inst hits
229 system.cpu0.dtb.inst_misses 0 # ITB inst misses
230 system.cpu0.dtb.read_hits 7857580 # DTB read hits
231 system.cpu0.dtb.read_misses 1898 # DTB read misses
232 system.cpu0.dtb.write_hits 6224259 # DTB write hits
233 system.cpu0.dtb.write_misses 1143 # DTB write misses
234 system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
235 system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
236 system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
237 system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
238 system.cpu0.dtb.flush_entries 1404 # Number of entries that have been flushed from TLB
239 system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
240 system.cpu0.dtb.prefetch_faults 79 # Number of TLB faults due to prefetch
241 system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
242 system.cpu0.dtb.perms_faults 191 # Number of TLB faults due to permissions restrictions
243 system.cpu0.dtb.read_accesses 7859478 # DTB read accesses
244 system.cpu0.dtb.write_accesses 6225402 # DTB write accesses
245 system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
246 system.cpu0.dtb.hits 14081839 # DTB hits
247 system.cpu0.dtb.misses 3041 # DTB misses
248 system.cpu0.dtb.accesses 14084880 # DTB accesses
249 system.cpu0.itb.inst_hits 35747911 # ITB inst hits
250 system.cpu0.itb.inst_misses 1204 # ITB inst misses
251 system.cpu0.itb.read_hits 0 # DTB read hits
252 system.cpu0.itb.read_misses 0 # DTB read misses
253 system.cpu0.itb.write_hits 0 # DTB write hits
254 system.cpu0.itb.write_misses 0 # DTB write misses
255 system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
256 system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
257 system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
258 system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
259 system.cpu0.itb.flush_entries 1262 # Number of entries that have been flushed from TLB
260 system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
261 system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
262 system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
263 system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
264 system.cpu0.itb.read_accesses 0 # DTB read accesses
265 system.cpu0.itb.write_accesses 0 # DTB write accesses
266 system.cpu0.itb.inst_accesses 35749115 # ITB inst accesses
267 system.cpu0.itb.hits 35747911 # DTB hits
268 system.cpu0.itb.misses 1204 # DTB misses
269 system.cpu0.itb.accesses 35749115 # DTB accesses
270 system.cpu0.numCycles 5337805216 # number of cpu cycles simulated
271 system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
272 system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
273 system.cpu0.num_insts 43969024 # Number of instructions executed
274 system.cpu0.num_int_alu_accesses 39881498 # Number of integer alu accesses
275 system.cpu0.num_fp_alu_accesses 4107 # Number of float alu accesses
276 system.cpu0.num_func_calls 977479 # number of times a function call or return occured
277 system.cpu0.num_conditional_control_insts 4512711 # number of instructions that are conditional controls
278 system.cpu0.num_int_insts 39881498 # number of integer instructions
279 system.cpu0.num_fp_insts 4107 # number of float instructions
280 system.cpu0.num_int_register_reads 225043856 # number of times the integer registers were read
281 system.cpu0.num_int_register_writes 43158045 # number of times the integer registers were written
282 system.cpu0.num_fp_register_reads 3851 # number of times the floating registers were read
283 system.cpu0.num_fp_register_writes 256 # number of times the floating registers were written
284 system.cpu0.num_mem_refs 14677999 # number of memory refs
285 system.cpu0.num_load_insts 8148547 # Number of load instructions
286 system.cpu0.num_store_insts 6529452 # Number of store instructions
287 system.cpu0.num_idle_cycles 5107410781.564784 # Number of idle cycles
288 system.cpu0.num_busy_cycles 230394434.435216 # Number of busy cycles
289 system.cpu0.not_idle_fraction 0.043163 # Percentage of non-idle cycles
290 system.cpu0.idle_fraction 0.956837 # Percentage of idle cycles
291 system.cpu0.kern.inst.arm 0 # number of arm instructions executed
292 system.cpu0.kern.inst.quiesce 38525 # number of quiesce instructions executed
293 system.cpu0.icache.replacements 380069 # number of replacements
294 system.cpu0.icache.tagsinuse 510.849663 # Cycle average of tags in use
295 system.cpu0.icache.total_refs 35367311 # Total number of references to valid blocks.
296 system.cpu0.icache.sampled_refs 380581 # Sample count of references to valid blocks.
297 system.cpu0.icache.avg_refs 92.929786 # Average number of references to valid blocks.
298 system.cpu0.icache.warmup_cycle 74921716000 # Cycle when the warmup percentage was hit.
299 system.cpu0.icache.occ_blocks::0 510.849663 # Average occupied blocks per context
300 system.cpu0.icache.occ_percent::0 0.997753 # Average percentage of cache occupancy
301 system.cpu0.icache.ReadReq_hits::0 35367311 # number of ReadReq hits
302 system.cpu0.icache.ReadReq_hits::total 35367311 # number of ReadReq hits
303 system.cpu0.icache.demand_hits::0 35367311 # number of demand (read+write) hits
304 system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits
305 system.cpu0.icache.demand_hits::total 35367311 # number of demand (read+write) hits
306 system.cpu0.icache.overall_hits::0 35367311 # number of overall hits
307 system.cpu0.icache.overall_hits::1 0 # number of overall hits
308 system.cpu0.icache.overall_hits::total 35367311 # number of overall hits
309 system.cpu0.icache.ReadReq_misses::0 380583 # number of ReadReq misses
310 system.cpu0.icache.ReadReq_misses::total 380583 # number of ReadReq misses
311 system.cpu0.icache.demand_misses::0 380583 # number of demand (read+write) misses
312 system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses
313 system.cpu0.icache.demand_misses::total 380583 # number of demand (read+write) misses
314 system.cpu0.icache.overall_misses::0 380583 # number of overall misses
315 system.cpu0.icache.overall_misses::1 0 # number of overall misses
316 system.cpu0.icache.overall_misses::total 380583 # number of overall misses
317 system.cpu0.icache.ReadReq_miss_latency 5651439000 # number of ReadReq miss cycles
318 system.cpu0.icache.demand_miss_latency 5651439000 # number of demand (read+write) miss cycles
319 system.cpu0.icache.overall_miss_latency 5651439000 # number of overall miss cycles
320 system.cpu0.icache.ReadReq_accesses::0 35747894 # number of ReadReq accesses(hits+misses)
321 system.cpu0.icache.ReadReq_accesses::total 35747894 # number of ReadReq accesses(hits+misses)
322 system.cpu0.icache.demand_accesses::0 35747894 # number of demand (read+write) accesses
323 system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses
324 system.cpu0.icache.demand_accesses::total 35747894 # number of demand (read+write) accesses
325 system.cpu0.icache.overall_accesses::0 35747894 # number of overall (read+write) accesses
326 system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses
327 system.cpu0.icache.overall_accesses::total 35747894 # number of overall (read+write) accesses
328 system.cpu0.icache.ReadReq_miss_rate::0 0.010646 # miss rate for ReadReq accesses
329 system.cpu0.icache.demand_miss_rate::0 0.010646 # miss rate for demand accesses
330 system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
331 system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses
332 system.cpu0.icache.overall_miss_rate::0 0.010646 # miss rate for overall accesses
333 system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
334 system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses
335 system.cpu0.icache.ReadReq_avg_miss_latency::0 14849.425749 # average ReadReq miss latency
336 system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
337 system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
338 system.cpu0.icache.demand_avg_miss_latency::0 14849.425749 # average overall miss latency
339 system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency
340 system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency
341 system.cpu0.icache.overall_avg_miss_latency::0 14849.425749 # average overall miss latency
342 system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency
343 system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency
344 system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
345 system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
346 system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
347 system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
348 system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
349 system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
350 system.cpu0.icache.fast_writes 0 # number of fast writes performed
351 system.cpu0.icache.cache_copies 0 # number of cache copies performed
352 system.cpu0.icache.writebacks 12960 # number of writebacks
353 system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
354 system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
355 system.cpu0.icache.ReadReq_mshr_misses 380583 # number of ReadReq MSHR misses
356 system.cpu0.icache.demand_mshr_misses 380583 # number of demand (read+write) MSHR misses
357 system.cpu0.icache.overall_mshr_misses 380583 # number of overall MSHR misses
358 system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
359 system.cpu0.icache.ReadReq_mshr_miss_latency 4509188500 # number of ReadReq MSHR miss cycles
360 system.cpu0.icache.demand_mshr_miss_latency 4509188500 # number of demand (read+write) MSHR miss cycles
361 system.cpu0.icache.overall_mshr_miss_latency 4509188500 # number of overall MSHR miss cycles
362 system.cpu0.icache.ReadReq_mshr_uncacheable_latency 351814000 # number of ReadReq MSHR uncacheable cycles
363 system.cpu0.icache.overall_mshr_uncacheable_latency 351814000 # number of overall MSHR uncacheable cycles
364 system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.010646 # mshr miss rate for ReadReq accesses
365 system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
366 system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
367 system.cpu0.icache.demand_mshr_miss_rate::0 0.010646 # mshr miss rate for demand accesses
368 system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
369 system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
370 system.cpu0.icache.overall_mshr_miss_rate::0 0.010646 # mshr miss rate for overall accesses
371 system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
372 system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
373 system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11848.108034 # average ReadReq mshr miss latency
374 system.cpu0.icache.demand_avg_mshr_miss_latency 11848.108034 # average overall mshr miss latency
375 system.cpu0.icache.overall_avg_mshr_miss_latency 11848.108034 # average overall mshr miss latency
376 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
377 system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
378 system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
379 system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
380 system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
381 system.cpu0.dcache.replacements 334596 # number of replacements
382 system.cpu0.dcache.tagsinuse 450.118381 # Cycle average of tags in use
383 system.cpu0.dcache.total_refs 12875674 # Total number of references to valid blocks.
384 system.cpu0.dcache.sampled_refs 335004 # Sample count of references to valid blocks.
385 system.cpu0.dcache.avg_refs 38.434389 # Average number of references to valid blocks.
386 system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit.
387 system.cpu0.dcache.occ_blocks::0 450.118381 # Average occupied blocks per context
388 system.cpu0.dcache.occ_percent::0 0.879137 # Average percentage of cache occupancy
389 system.cpu0.dcache.ReadReq_hits::0 7428609 # number of ReadReq hits
390 system.cpu0.dcache.ReadReq_hits::total 7428609 # number of ReadReq hits
391 system.cpu0.dcache.WriteReq_hits::0 5172633 # number of WriteReq hits
392 system.cpu0.dcache.WriteReq_hits::total 5172633 # number of WriteReq hits
393 system.cpu0.dcache.LoadLockedReq_hits::0 126778 # number of LoadLockedReq hits
394 system.cpu0.dcache.LoadLockedReq_hits::total 126778 # number of LoadLockedReq hits
395 system.cpu0.dcache.StoreCondReq_hits::0 127996 # number of StoreCondReq hits
396 system.cpu0.dcache.StoreCondReq_hits::total 127996 # number of StoreCondReq hits
397 system.cpu0.dcache.demand_hits::0 12601242 # number of demand (read+write) hits
398 system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits
399 system.cpu0.dcache.demand_hits::total 12601242 # number of demand (read+write) hits
400 system.cpu0.dcache.overall_hits::0 12601242 # number of overall hits
401 system.cpu0.dcache.overall_hits::1 0 # number of overall hits
402 system.cpu0.dcache.overall_hits::total 12601242 # number of overall hits
403 system.cpu0.dcache.ReadReq_misses::0 217330 # number of ReadReq misses
404 system.cpu0.dcache.ReadReq_misses::total 217330 # number of ReadReq misses
405 system.cpu0.dcache.WriteReq_misses::0 155538 # number of WriteReq misses
406 system.cpu0.dcache.WriteReq_misses::total 155538 # number of WriteReq misses
407 system.cpu0.dcache.LoadLockedReq_misses::0 9456 # number of LoadLockedReq misses
408 system.cpu0.dcache.LoadLockedReq_misses::total 9456 # number of LoadLockedReq misses
409 system.cpu0.dcache.StoreCondReq_misses::0 8189 # number of StoreCondReq misses
410 system.cpu0.dcache.StoreCondReq_misses::total 8189 # number of StoreCondReq misses
411 system.cpu0.dcache.demand_misses::0 372868 # number of demand (read+write) misses
412 system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses
413 system.cpu0.dcache.demand_misses::total 372868 # number of demand (read+write) misses
414 system.cpu0.dcache.overall_misses::0 372868 # number of overall misses
415 system.cpu0.dcache.overall_misses::1 0 # number of overall misses
416 system.cpu0.dcache.overall_misses::total 372868 # number of overall misses
417 system.cpu0.dcache.ReadReq_miss_latency 3330686000 # number of ReadReq miss cycles
418 system.cpu0.dcache.WriteReq_miss_latency 6317758500 # number of WriteReq miss cycles
419 system.cpu0.dcache.LoadLockedReq_miss_latency 100249000 # number of LoadLockedReq miss cycles
420 system.cpu0.dcache.StoreCondReq_miss_latency 70240000 # number of StoreCondReq miss cycles
421 system.cpu0.dcache.demand_miss_latency 9648444500 # number of demand (read+write) miss cycles
422 system.cpu0.dcache.overall_miss_latency 9648444500 # number of overall miss cycles
423 system.cpu0.dcache.ReadReq_accesses::0 7645939 # number of ReadReq accesses(hits+misses)
424 system.cpu0.dcache.ReadReq_accesses::total 7645939 # number of ReadReq accesses(hits+misses)
425 system.cpu0.dcache.WriteReq_accesses::0 5328171 # number of WriteReq accesses(hits+misses)
426 system.cpu0.dcache.WriteReq_accesses::total 5328171 # number of WriteReq accesses(hits+misses)
427 system.cpu0.dcache.LoadLockedReq_accesses::0 136234 # number of LoadLockedReq accesses(hits+misses)
428 system.cpu0.dcache.LoadLockedReq_accesses::total 136234 # number of LoadLockedReq accesses(hits+misses)
429 system.cpu0.dcache.StoreCondReq_accesses::0 136185 # number of StoreCondReq accesses(hits+misses)
430 system.cpu0.dcache.StoreCondReq_accesses::total 136185 # number of StoreCondReq accesses(hits+misses)
431 system.cpu0.dcache.demand_accesses::0 12974110 # number of demand (read+write) accesses
432 system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
433 system.cpu0.dcache.demand_accesses::total 12974110 # number of demand (read+write) accesses
434 system.cpu0.dcache.overall_accesses::0 12974110 # number of overall (read+write) accesses
435 system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
436 system.cpu0.dcache.overall_accesses::total 12974110 # number of overall (read+write) accesses
437 system.cpu0.dcache.ReadReq_miss_rate::0 0.028424 # miss rate for ReadReq accesses
438 system.cpu0.dcache.WriteReq_miss_rate::0 0.029192 # miss rate for WriteReq accesses
439 system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.069410 # miss rate for LoadLockedReq accesses
440 system.cpu0.dcache.StoreCondReq_miss_rate::0 0.060131 # miss rate for StoreCondReq accesses
441 system.cpu0.dcache.demand_miss_rate::0 0.028739 # miss rate for demand accesses
442 system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
443 system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
444 system.cpu0.dcache.overall_miss_rate::0 0.028739 # miss rate for overall accesses
445 system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
446 system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
447 system.cpu0.dcache.ReadReq_avg_miss_latency::0 15325.477385 # average ReadReq miss latency
448 system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
449 system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
450 system.cpu0.dcache.WriteReq_avg_miss_latency::0 40618.745901 # average WriteReq miss latency
451 system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
452 system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
453 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 10601.628596 # average LoadLockedReq miss latency
454 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
455 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
456 system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 8577.359873 # average StoreCondReq miss latency
457 system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
458 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
459 system.cpu0.dcache.demand_avg_miss_latency::0 25876.300728 # average overall miss latency
460 system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
461 system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency
462 system.cpu0.dcache.overall_avg_miss_latency::0 25876.300728 # average overall miss latency
463 system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
464 system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency
465 system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
466 system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
467 system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
468 system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
469 system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
470 system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
471 system.cpu0.dcache.fast_writes 0 # number of fast writes performed
472 system.cpu0.dcache.cache_copies 0 # number of cache copies performed
473 system.cpu0.dcache.writebacks 294891 # number of writebacks
474 system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
475 system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
476 system.cpu0.dcache.ReadReq_mshr_misses 217330 # number of ReadReq MSHR misses
477 system.cpu0.dcache.WriteReq_mshr_misses 155538 # number of WriteReq MSHR misses
478 system.cpu0.dcache.LoadLockedReq_mshr_misses 9456 # number of LoadLockedReq MSHR misses
479 system.cpu0.dcache.StoreCondReq_mshr_misses 8184 # number of StoreCondReq MSHR misses
480 system.cpu0.dcache.demand_mshr_misses 372868 # number of demand (read+write) MSHR misses
481 system.cpu0.dcache.overall_mshr_misses 372868 # number of overall MSHR misses
482 system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
483 system.cpu0.dcache.ReadReq_mshr_miss_latency 2678673500 # number of ReadReq MSHR miss cycles
484 system.cpu0.dcache.WriteReq_mshr_miss_latency 5851029000 # number of WriteReq MSHR miss cycles
485 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 71881000 # number of LoadLockedReq MSHR miss cycles
486 system.cpu0.dcache.StoreCondReq_mshr_miss_latency 45691000 # number of StoreCondReq MSHR miss cycles
487 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles
488 system.cpu0.dcache.demand_mshr_miss_latency 8529702500 # number of demand (read+write) MSHR miss cycles
489 system.cpu0.dcache.overall_mshr_miss_latency 8529702500 # number of overall MSHR miss cycles
490 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 9171180500 # number of ReadReq MSHR uncacheable cycles
491 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 40129379500 # number of WriteReq MSHR uncacheable cycles
492 system.cpu0.dcache.overall_mshr_uncacheable_latency 49300560000 # number of overall MSHR uncacheable cycles
493 system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028424 # mshr miss rate for ReadReq accesses
494 system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
495 system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
496 system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.029192 # mshr miss rate for WriteReq accesses
497 system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
498 system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
499 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.069410 # mshr miss rate for LoadLockedReq accesses
500 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
501 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
502 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.060095 # mshr miss rate for StoreCondReq accesses
503 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
504 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
505 system.cpu0.dcache.demand_mshr_miss_rate::0 0.028739 # mshr miss rate for demand accesses
506 system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
507 system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
508 system.cpu0.dcache.overall_mshr_miss_rate::0 0.028739 # mshr miss rate for overall accesses
509 system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
510 system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
511 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12325.373855 # average ReadReq mshr miss latency
512 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37618.003318 # average WriteReq mshr miss latency
513 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 7601.628596 # average LoadLockedReq mshr miss latency
514 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 5582.966764 # average StoreCondReq mshr miss latency
515 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency
516 system.cpu0.dcache.demand_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency
517 system.cpu0.dcache.overall_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency
518 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
519 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
520 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
521 system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
522 system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
523 system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
524 system.cpu1.dtb.inst_hits 0 # ITB inst hits
525 system.cpu1.dtb.inst_misses 0 # ITB inst misses
526 system.cpu1.dtb.read_hits 7762496 # DTB read hits
527 system.cpu1.dtb.read_misses 5432 # DTB read misses
528 system.cpu1.dtb.write_hits 5411648 # DTB write hits
529 system.cpu1.dtb.write_misses 1096 # DTB write misses
530 system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
531 system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
532 system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
533 system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
534 system.cpu1.dtb.flush_entries 2346 # Number of entries that have been flushed from TLB
535 system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
536 system.cpu1.dtb.prefetch_faults 166 # Number of TLB faults due to prefetch
537 system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
538 system.cpu1.dtb.perms_faults 261 # Number of TLB faults due to permissions restrictions
539 system.cpu1.dtb.read_accesses 7767928 # DTB read accesses
540 system.cpu1.dtb.write_accesses 5412744 # DTB write accesses
541 system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
542 system.cpu1.dtb.hits 13174144 # DTB hits
543 system.cpu1.dtb.misses 6528 # DTB misses
544 system.cpu1.dtb.accesses 13180672 # DTB accesses
545 system.cpu1.itb.inst_hits 26848280 # ITB inst hits
546 system.cpu1.itb.inst_misses 3154 # ITB inst misses
547 system.cpu1.itb.read_hits 0 # DTB read hits
548 system.cpu1.itb.read_misses 0 # DTB read misses
549 system.cpu1.itb.write_hits 0 # DTB write hits
550 system.cpu1.itb.write_misses 0 # DTB write misses
551 system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
552 system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
553 system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
554 system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
555 system.cpu1.itb.flush_entries 1544 # Number of entries that have been flushed from TLB
556 system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
557 system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
558 system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
559 system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
560 system.cpu1.itb.read_accesses 0 # DTB read accesses
561 system.cpu1.itb.write_accesses 0 # DTB write accesses
562 system.cpu1.itb.inst_accesses 26851434 # ITB inst accesses
563 system.cpu1.itb.hits 26848280 # DTB hits
564 system.cpu1.itb.misses 3154 # DTB misses
565 system.cpu1.itb.accesses 26851434 # DTB accesses
566 system.cpu1.numCycles 5339222450 # number of cpu cycles simulated
567 system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
568 system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
569 system.cpu1.num_insts 34444935 # Number of instructions executed
570 system.cpu1.num_int_alu_accesses 31033253 # Number of integer alu accesses
571 system.cpu1.num_fp_alu_accesses 5714 # Number of float alu accesses
572 system.cpu1.num_func_calls 1093852 # number of times a function call or return occured
573 system.cpu1.num_conditional_control_insts 3362553 # number of instructions that are conditional controls
574 system.cpu1.num_int_insts 31033253 # number of integer instructions
575 system.cpu1.num_fp_insts 5714 # number of float instructions
576 system.cpu1.num_int_register_reads 181157193 # number of times the integer registers were read
577 system.cpu1.num_int_register_writes 32585304 # number of times the integer registers were written
578 system.cpu1.num_fp_register_reads 3770 # number of times the floating registers were read
579 system.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written
580 system.cpu1.num_mem_refs 13796843 # number of memory refs
581 system.cpu1.num_load_insts 8139019 # Number of load instructions
582 system.cpu1.num_store_insts 5657824 # Number of store instructions
583 system.cpu1.num_idle_cycles 4950307250.068146 # Number of idle cycles
584 system.cpu1.num_busy_cycles 388915199.931854 # Number of busy cycles
585 system.cpu1.not_idle_fraction 0.072841 # Percentage of non-idle cycles
586 system.cpu1.idle_fraction 0.927159 # Percentage of idle cycles
587 system.cpu1.kern.inst.arm 0 # number of arm instructions executed
588 system.cpu1.kern.inst.quiesce 53838 # number of quiesce instructions executed
589 system.cpu1.icache.replacements 508221 # number of replacements
590 system.cpu1.icache.tagsinuse 497.375159 # Cycle average of tags in use
591 system.cpu1.icache.total_refs 26339543 # Total number of references to valid blocks.
592 system.cpu1.icache.sampled_refs 508733 # Sample count of references to valid blocks.
593 system.cpu1.icache.avg_refs 51.774788 # Average number of references to valid blocks.
594 system.cpu1.icache.warmup_cycle 191336880000 # Cycle when the warmup percentage was hit.
595 system.cpu1.icache.occ_blocks::0 497.375159 # Average occupied blocks per context
596 system.cpu1.icache.occ_percent::0 0.971436 # Average percentage of cache occupancy
597 system.cpu1.icache.ReadReq_hits::0 26339543 # number of ReadReq hits
598 system.cpu1.icache.ReadReq_hits::total 26339543 # number of ReadReq hits
599 system.cpu1.icache.demand_hits::0 26339543 # number of demand (read+write) hits
600 system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits
601 system.cpu1.icache.demand_hits::total 26339543 # number of demand (read+write) hits
602 system.cpu1.icache.overall_hits::0 26339543 # number of overall hits
603 system.cpu1.icache.overall_hits::1 0 # number of overall hits
604 system.cpu1.icache.overall_hits::total 26339543 # number of overall hits
605 system.cpu1.icache.ReadReq_misses::0 508733 # number of ReadReq misses
606 system.cpu1.icache.ReadReq_misses::total 508733 # number of ReadReq misses
607 system.cpu1.icache.demand_misses::0 508733 # number of demand (read+write) misses
608 system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses
609 system.cpu1.icache.demand_misses::total 508733 # number of demand (read+write) misses
610 system.cpu1.icache.overall_misses::0 508733 # number of overall misses
611 system.cpu1.icache.overall_misses::1 0 # number of overall misses
612 system.cpu1.icache.overall_misses::total 508733 # number of overall misses
613 system.cpu1.icache.ReadReq_miss_latency 7436442000 # number of ReadReq miss cycles
614 system.cpu1.icache.demand_miss_latency 7436442000 # number of demand (read+write) miss cycles
615 system.cpu1.icache.overall_miss_latency 7436442000 # number of overall miss cycles
616 system.cpu1.icache.ReadReq_accesses::0 26848276 # number of ReadReq accesses(hits+misses)
617 system.cpu1.icache.ReadReq_accesses::total 26848276 # number of ReadReq accesses(hits+misses)
618 system.cpu1.icache.demand_accesses::0 26848276 # number of demand (read+write) accesses
619 system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses
620 system.cpu1.icache.demand_accesses::total 26848276 # number of demand (read+write) accesses
621 system.cpu1.icache.overall_accesses::0 26848276 # number of overall (read+write) accesses
622 system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses
623 system.cpu1.icache.overall_accesses::total 26848276 # number of overall (read+write) accesses
624 system.cpu1.icache.ReadReq_miss_rate::0 0.018948 # miss rate for ReadReq accesses
625 system.cpu1.icache.demand_miss_rate::0 0.018948 # miss rate for demand accesses
626 system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
627 system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses
628 system.cpu1.icache.overall_miss_rate::0 0.018948 # miss rate for overall accesses
629 system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
630 system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses
631 system.cpu1.icache.ReadReq_avg_miss_latency::0 14617.573462 # average ReadReq miss latency
632 system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
633 system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
634 system.cpu1.icache.demand_avg_miss_latency::0 14617.573462 # average overall miss latency
635 system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency
636 system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency
637 system.cpu1.icache.overall_avg_miss_latency::0 14617.573462 # average overall miss latency
638 system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency
639 system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency
640 system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
641 system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
642 system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
643 system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
644 system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
645 system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
646 system.cpu1.icache.fast_writes 0 # number of fast writes performed
647 system.cpu1.icache.cache_copies 0 # number of cache copies performed
648 system.cpu1.icache.writebacks 27998 # number of writebacks
649 system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
650 system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
651 system.cpu1.icache.ReadReq_mshr_misses 508733 # number of ReadReq MSHR misses
652 system.cpu1.icache.demand_mshr_misses 508733 # number of demand (read+write) MSHR misses
653 system.cpu1.icache.overall_mshr_misses 508733 # number of overall MSHR misses
654 system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
655 system.cpu1.icache.ReadReq_mshr_miss_latency 5908060000 # number of ReadReq MSHR miss cycles
656 system.cpu1.icache.demand_mshr_miss_latency 5908060000 # number of demand (read+write) MSHR miss cycles
657 system.cpu1.icache.overall_mshr_miss_latency 5908060000 # number of overall MSHR miss cycles
658 system.cpu1.icache.ReadReq_mshr_uncacheable_latency 5250000 # number of ReadReq MSHR uncacheable cycles
659 system.cpu1.icache.overall_mshr_uncacheable_latency 5250000 # number of overall MSHR uncacheable cycles
660 system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.018948 # mshr miss rate for ReadReq accesses
661 system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
662 system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
663 system.cpu1.icache.demand_mshr_miss_rate::0 0.018948 # mshr miss rate for demand accesses
664 system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
665 system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
666 system.cpu1.icache.overall_mshr_miss_rate::0 0.018948 # mshr miss rate for overall accesses
667 system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
668 system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
669 system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11613.282409 # average ReadReq mshr miss latency
670 system.cpu1.icache.demand_avg_mshr_miss_latency 11613.282409 # average overall mshr miss latency
671 system.cpu1.icache.overall_avg_mshr_miss_latency 11613.282409 # average overall mshr miss latency
672 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
673 system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
674 system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
675 system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
676 system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
677 system.cpu1.dcache.replacements 295754 # number of replacements
678 system.cpu1.dcache.tagsinuse 467.166427 # Cycle average of tags in use
679 system.cpu1.dcache.total_refs 11737107 # Total number of references to valid blocks.
680 system.cpu1.dcache.sampled_refs 296266 # Sample count of references to valid blocks.
681 system.cpu1.dcache.avg_refs 39.616787 # Average number of references to valid blocks.
682 system.cpu1.dcache.warmup_cycle 75924171000 # Cycle when the warmup percentage was hit.
683 system.cpu1.dcache.occ_blocks::0 467.166427 # Average occupied blocks per context
684 system.cpu1.dcache.occ_percent::0 0.912434 # Average percentage of cache occupancy
685 system.cpu1.dcache.ReadReq_hits::0 6345290 # number of ReadReq hits
686 system.cpu1.dcache.ReadReq_hits::total 6345290 # number of ReadReq hits
687 system.cpu1.dcache.WriteReq_hits::0 5152610 # number of WriteReq hits
688 system.cpu1.dcache.WriteReq_hits::total 5152610 # number of WriteReq hits
689 system.cpu1.dcache.LoadLockedReq_hits::0 104795 # number of LoadLockedReq hits
690 system.cpu1.dcache.LoadLockedReq_hits::total 104795 # number of LoadLockedReq hits
691 system.cpu1.dcache.StoreCondReq_hits::0 106403 # number of StoreCondReq hits
692 system.cpu1.dcache.StoreCondReq_hits::total 106403 # number of StoreCondReq hits
693 system.cpu1.dcache.demand_hits::0 11497900 # number of demand (read+write) hits
694 system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
695 system.cpu1.dcache.demand_hits::total 11497900 # number of demand (read+write) hits
696 system.cpu1.dcache.overall_hits::0 11497900 # number of overall hits
697 system.cpu1.dcache.overall_hits::1 0 # number of overall hits
698 system.cpu1.dcache.overall_hits::total 11497900 # number of overall hits
699 system.cpu1.dcache.ReadReq_misses::0 188245 # number of ReadReq misses
700 system.cpu1.dcache.ReadReq_misses::total 188245 # number of ReadReq misses
701 system.cpu1.dcache.WriteReq_misses::0 137493 # number of WriteReq misses
702 system.cpu1.dcache.WriteReq_misses::total 137493 # number of WriteReq misses
703 system.cpu1.dcache.LoadLockedReq_misses::0 11557 # number of LoadLockedReq misses
704 system.cpu1.dcache.LoadLockedReq_misses::total 11557 # number of LoadLockedReq misses
705 system.cpu1.dcache.StoreCondReq_misses::0 9906 # number of StoreCondReq misses
706 system.cpu1.dcache.StoreCondReq_misses::total 9906 # number of StoreCondReq misses
707 system.cpu1.dcache.demand_misses::0 325738 # number of demand (read+write) misses
708 system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
709 system.cpu1.dcache.demand_misses::total 325738 # number of demand (read+write) misses
710 system.cpu1.dcache.overall_misses::0 325738 # number of overall misses
711 system.cpu1.dcache.overall_misses::1 0 # number of overall misses
712 system.cpu1.dcache.overall_misses::total 325738 # number of overall misses
713 system.cpu1.dcache.ReadReq_miss_latency 2729023500 # number of ReadReq miss cycles
714 system.cpu1.dcache.WriteReq_miss_latency 4123985000 # number of WriteReq miss cycles
715 system.cpu1.dcache.LoadLockedReq_miss_latency 131721000 # number of LoadLockedReq miss cycles
716 system.cpu1.dcache.StoreCondReq_miss_latency 82493000 # number of StoreCondReq miss cycles
717 system.cpu1.dcache.demand_miss_latency 6853008500 # number of demand (read+write) miss cycles
718 system.cpu1.dcache.overall_miss_latency 6853008500 # number of overall miss cycles
719 system.cpu1.dcache.ReadReq_accesses::0 6533535 # number of ReadReq accesses(hits+misses)
720 system.cpu1.dcache.ReadReq_accesses::total 6533535 # number of ReadReq accesses(hits+misses)
721 system.cpu1.dcache.WriteReq_accesses::0 5290103 # number of WriteReq accesses(hits+misses)
722 system.cpu1.dcache.WriteReq_accesses::total 5290103 # number of WriteReq accesses(hits+misses)
723 system.cpu1.dcache.LoadLockedReq_accesses::0 116352 # number of LoadLockedReq accesses(hits+misses)
724 system.cpu1.dcache.LoadLockedReq_accesses::total 116352 # number of LoadLockedReq accesses(hits+misses)
725 system.cpu1.dcache.StoreCondReq_accesses::0 116309 # number of StoreCondReq accesses(hits+misses)
726 system.cpu1.dcache.StoreCondReq_accesses::total 116309 # number of StoreCondReq accesses(hits+misses)
727 system.cpu1.dcache.demand_accesses::0 11823638 # number of demand (read+write) accesses
728 system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
729 system.cpu1.dcache.demand_accesses::total 11823638 # number of demand (read+write) accesses
730 system.cpu1.dcache.overall_accesses::0 11823638 # number of overall (read+write) accesses
731 system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
732 system.cpu1.dcache.overall_accesses::total 11823638 # number of overall (read+write) accesses
733 system.cpu1.dcache.ReadReq_miss_rate::0 0.028812 # miss rate for ReadReq accesses
734 system.cpu1.dcache.WriteReq_miss_rate::0 0.025991 # miss rate for WriteReq accesses
735 system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.099328 # miss rate for LoadLockedReq accesses
736 system.cpu1.dcache.StoreCondReq_miss_rate::0 0.085170 # miss rate for StoreCondReq accesses
737 system.cpu1.dcache.demand_miss_rate::0 0.027550 # miss rate for demand accesses
738 system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
739 system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
740 system.cpu1.dcache.overall_miss_rate::0 0.027550 # miss rate for overall accesses
741 system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
742 system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
743 system.cpu1.dcache.ReadReq_avg_miss_latency::0 14497.189832 # average ReadReq miss latency
744 system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
745 system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
746 system.cpu1.dcache.WriteReq_avg_miss_latency::0 29994.145156 # average WriteReq miss latency
747 system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
748 system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
749 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11397.508004 # average LoadLockedReq miss latency
750 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
751 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
752 system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 8327.579245 # average StoreCondReq miss latency
753 system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
754 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
755 system.cpu1.dcache.demand_avg_miss_latency::0 21038.406634 # average overall miss latency
756 system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
757 system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency
758 system.cpu1.dcache.overall_avg_miss_latency::0 21038.406634 # average overall miss latency
759 system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
760 system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency
761 system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
762 system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
763 system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
764 system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
765 system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
766 system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
767 system.cpu1.dcache.fast_writes 0 # number of fast writes performed
768 system.cpu1.dcache.cache_copies 0 # number of cache copies performed
769 system.cpu1.dcache.writebacks 253551 # number of writebacks
770 system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
771 system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
772 system.cpu1.dcache.ReadReq_mshr_misses 188245 # number of ReadReq MSHR misses
773 system.cpu1.dcache.WriteReq_mshr_misses 137493 # number of WriteReq MSHR misses
774 system.cpu1.dcache.LoadLockedReq_mshr_misses 11557 # number of LoadLockedReq MSHR misses
775 system.cpu1.dcache.StoreCondReq_mshr_misses 9900 # number of StoreCondReq MSHR misses
776 system.cpu1.dcache.demand_mshr_misses 325738 # number of demand (read+write) MSHR misses
777 system.cpu1.dcache.overall_mshr_misses 325738 # number of overall MSHR misses
778 system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
779 system.cpu1.dcache.ReadReq_mshr_miss_latency 2164153000 # number of ReadReq MSHR miss cycles
780 system.cpu1.dcache.WriteReq_mshr_miss_latency 3711466500 # number of WriteReq MSHR miss cycles
781 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 97050000 # number of LoadLockedReq MSHR miss cycles
782 system.cpu1.dcache.StoreCondReq_mshr_miss_latency 52793000 # number of StoreCondReq MSHR miss cycles
783 system.cpu1.dcache.demand_mshr_miss_latency 5875619500 # number of demand (read+write) MSHR miss cycles
784 system.cpu1.dcache.overall_mshr_miss_latency 5875619500 # number of overall MSHR miss cycles
785 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 137931975000 # number of ReadReq MSHR uncacheable cycles
786 system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 470526000 # number of WriteReq MSHR uncacheable cycles
787 system.cpu1.dcache.overall_mshr_uncacheable_latency 138402501000 # number of overall MSHR uncacheable cycles
788 system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.028812 # mshr miss rate for ReadReq accesses
789 system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
790 system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
791 system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.025991 # mshr miss rate for WriteReq accesses
792 system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
793 system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
794 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.099328 # mshr miss rate for LoadLockedReq accesses
795 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
796 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
797 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.085118 # mshr miss rate for StoreCondReq accesses
798 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
799 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
800 system.cpu1.dcache.demand_mshr_miss_rate::0 0.027550 # mshr miss rate for demand accesses
801 system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
802 system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
803 system.cpu1.dcache.overall_mshr_miss_rate::0 0.027550 # mshr miss rate for overall accesses
804 system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
805 system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
806 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11496.470026 # average ReadReq mshr miss latency
807 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 26993.857869 # average WriteReq mshr miss latency
808 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8397.508004 # average LoadLockedReq mshr miss latency
809 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 5332.626263 # average StoreCondReq mshr miss latency
810 system.cpu1.dcache.demand_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency
811 system.cpu1.dcache.overall_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency
812 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
813 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
814 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
815 system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
816 system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
817 system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
818 system.iocache.replacements 0 # number of replacements
819 system.iocache.tagsinuse 0 # Cycle average of tags in use
820 system.iocache.total_refs 0 # Total number of references to valid blocks.
821 system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
822 system.iocache.avg_refs no_value # Average number of references to valid blocks.
823 system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
824 system.iocache.demand_hits::0 0 # number of demand (read+write) hits
825 system.iocache.demand_hits::1 0 # number of demand (read+write) hits
826 system.iocache.demand_hits::total 0 # number of demand (read+write) hits
827 system.iocache.overall_hits::0 0 # number of overall hits
828 system.iocache.overall_hits::1 0 # number of overall hits
829 system.iocache.overall_hits::total 0 # number of overall hits
830 system.iocache.demand_misses::0 0 # number of demand (read+write) misses
831 system.iocache.demand_misses::1 0 # number of demand (read+write) misses
832 system.iocache.demand_misses::total 0 # number of demand (read+write) misses
833 system.iocache.overall_misses::0 0 # number of overall misses
834 system.iocache.overall_misses::1 0 # number of overall misses
835 system.iocache.overall_misses::total 0 # number of overall misses
836 system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
837 system.iocache.overall_miss_latency 0 # number of overall miss cycles
838 system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
839 system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
840 system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
841 system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
842 system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
843 system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
844 system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
845 system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
846 system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
847 system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
848 system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
849 system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
850 system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
851 system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
852 system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
853 system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
854 system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
855 system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
856 system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
857 system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
858 system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
859 system.iocache.blocked::no_targets 0 # number of cycles access was blocked
860 system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
861 system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
862 system.iocache.fast_writes 0 # number of fast writes performed
863 system.iocache.cache_copies 0 # number of cache copies performed
864 system.iocache.writebacks 0 # number of writebacks
865 system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
866 system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
867 system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
868 system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
869 system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
870 system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
871 system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
872 system.iocache.ReadReq_mshr_uncacheable_latency 1342252853622 # number of ReadReq MSHR uncacheable cycles
873 system.iocache.overall_mshr_uncacheable_latency 1342252853622 # number of overall MSHR uncacheable cycles
874 system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
875 system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
876 system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
877 system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
878 system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
879 system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
880 system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
881 system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
882 system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
883 system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
884 system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
885 system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
886 system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
888 ---------- End Simulation Statistics ----------
projects / gem5.git / blob