5 time_sync_period=100000000000
6 time_sync_spin_threshold=100000000
10 children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
12 physmem=system.physmem
13 work_begin_ckpt_count=0
14 work_begin_cpu_id_exit=-1
15 work_begin_exit_count=0
16 work_cpus_ckpt_count=0
23 children=dcache dtb icache itb tracer workload
27 defer_registration=false
28 do_checkpoint_insts=true
29 do_statistics_insts=true
32 function_trace_start=0
34 max_insts_all_threads=0
35 max_insts_any_thread=0
36 max_loads_all_threads=0
37 max_loads_any_thread=0
42 tracer=system.cpu0.tracer
43 workload=system.cpu0.workload
44 dcache_port=system.cpu0.dcache.cpu_side
45 icache_port=system.cpu0.icache.cpu_side
49 addr_range=0:18446744073709551615
59 prefetch_data_accesses_only=false
61 prefetch_latency=10000
62 prefetch_on_access=false
63 prefetch_past_page=false
65 prefetch_serial_squash=false
66 prefetch_use_cpu_id=true
68 prioritizeRequests=false
76 cpu_side=system.cpu0.dcache_port
77 mem_side=system.toL2Bus.port[2]
85 addr_range=0:18446744073709551615
95 prefetch_data_accesses_only=false
97 prefetch_latency=10000
98 prefetch_on_access=false
99 prefetch_past_page=false
101 prefetch_serial_squash=false
102 prefetch_use_cpu_id=true
104 prioritizeRequests=false
112 cpu_side=system.cpu0.icache_port
113 mem_side=system.toL2Bus.port[1]
122 [system.cpu0.workload]
130 executable=/chips/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
133 max_stack_size=67108864
143 children=dcache dtb icache itb tracer
147 defer_registration=false
148 do_checkpoint_insts=true
149 do_statistics_insts=true
152 function_trace_start=0
154 max_insts_all_threads=0
155 max_insts_any_thread=0
156 max_loads_all_threads=0
157 max_loads_any_thread=0
162 tracer=system.cpu1.tracer
163 workload=system.cpu0.workload
164 dcache_port=system.cpu1.dcache.cpu_side
165 icache_port=system.cpu1.icache.cpu_side
169 addr_range=0:18446744073709551615
179 prefetch_data_accesses_only=false
181 prefetch_latency=10000
182 prefetch_on_access=false
183 prefetch_past_page=false
185 prefetch_serial_squash=false
186 prefetch_use_cpu_id=true
188 prioritizeRequests=false
196 cpu_side=system.cpu1.dcache_port
197 mem_side=system.toL2Bus.port[4]
205 addr_range=0:18446744073709551615
215 prefetch_data_accesses_only=false
217 prefetch_latency=10000
218 prefetch_on_access=false
219 prefetch_past_page=false
221 prefetch_serial_squash=false
222 prefetch_use_cpu_id=true
224 prioritizeRequests=false
232 cpu_side=system.cpu1.icache_port
233 mem_side=system.toL2Bus.port[3]
244 children=dcache dtb icache itb tracer
248 defer_registration=false
249 do_checkpoint_insts=true
250 do_statistics_insts=true
253 function_trace_start=0
255 max_insts_all_threads=0
256 max_insts_any_thread=0
257 max_loads_all_threads=0
258 max_loads_any_thread=0
263 tracer=system.cpu2.tracer
264 workload=system.cpu0.workload
265 dcache_port=system.cpu2.dcache.cpu_side
266 icache_port=system.cpu2.icache.cpu_side
270 addr_range=0:18446744073709551615
280 prefetch_data_accesses_only=false
282 prefetch_latency=10000
283 prefetch_on_access=false
284 prefetch_past_page=false
286 prefetch_serial_squash=false
287 prefetch_use_cpu_id=true
289 prioritizeRequests=false
297 cpu_side=system.cpu2.dcache_port
298 mem_side=system.toL2Bus.port[6]
306 addr_range=0:18446744073709551615
316 prefetch_data_accesses_only=false
318 prefetch_latency=10000
319 prefetch_on_access=false
320 prefetch_past_page=false
322 prefetch_serial_squash=false
323 prefetch_use_cpu_id=true
325 prioritizeRequests=false
333 cpu_side=system.cpu2.icache_port
334 mem_side=system.toL2Bus.port[5]
345 children=dcache dtb icache itb tracer
349 defer_registration=false
350 do_checkpoint_insts=true
351 do_statistics_insts=true
354 function_trace_start=0
356 max_insts_all_threads=0
357 max_insts_any_thread=0
358 max_loads_all_threads=0
359 max_loads_any_thread=0
364 tracer=system.cpu3.tracer
365 workload=system.cpu0.workload
366 dcache_port=system.cpu3.dcache.cpu_side
367 icache_port=system.cpu3.icache.cpu_side
371 addr_range=0:18446744073709551615
381 prefetch_data_accesses_only=false
383 prefetch_latency=10000
384 prefetch_on_access=false
385 prefetch_past_page=false
387 prefetch_serial_squash=false
388 prefetch_use_cpu_id=true
390 prioritizeRequests=false
398 cpu_side=system.cpu3.dcache_port
399 mem_side=system.toL2Bus.port[8]
407 addr_range=0:18446744073709551615
417 prefetch_data_accesses_only=false
419 prefetch_latency=10000
420 prefetch_on_access=false
421 prefetch_past_page=false
423 prefetch_serial_squash=false
424 prefetch_use_cpu_id=true
426 prioritizeRequests=false
434 cpu_side=system.cpu3.icache_port
435 mem_side=system.toL2Bus.port[7]
446 addr_range=0:18446744073709551615
456 prefetch_data_accesses_only=false
458 prefetch_latency=100000
459 prefetch_on_access=false
460 prefetch_past_page=false
462 prefetch_serial_squash=false
463 prefetch_use_cpu_id=true
465 prioritizeRequests=false
473 cpu_side=system.toL2Bus.port[0]
474 mem_side=system.membus.port[0]
482 use_default_range=false
484 port=system.l2c.mem_side system.physmem.port[0]
494 port=system.membus.port[1]
502 use_default_range=false
504 port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side